mirror of https://gitee.com/openkylin/qemu.git
target/riscv: Fix bug in getting trap cause name for trace_riscv_trap
When the cause number is equal to or greater than 23, print "(unknown)" in trace_riscv_trap. The max valid number of riscv_excp_names is 23, so the last excpetion "guest_store_page_fault" can not be printed. In addition, the current check of cause is invalid for riscv_intr_names. So introduce riscv_cpu_get_trap_name to get the trap cause name. Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200814035819.1214-1-jiangyifei@huawei.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -96,6 +96,17 @@ const char * const riscv_intr_names[] = {
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"reserved"
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"reserved"
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};
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};
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const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
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{
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if (async) {
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return (cause < ARRAY_SIZE(riscv_intr_names)) ?
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riscv_intr_names[cause] : "(unknown)";
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} else {
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return (cause < ARRAY_SIZE(riscv_excp_names)) ?
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riscv_excp_names[cause] : "(unknown)";
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}
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}
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static void set_misa(CPURISCVState *env, target_ulong misa)
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static void set_misa(CPURISCVState *env, target_ulong misa)
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{
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{
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env->misa_mask = env->misa = misa;
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env->misa_mask = env->misa = misa;
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@ -312,6 +312,7 @@ extern const char * const riscv_fpr_regnames[];
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extern const char * const riscv_excp_names[];
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extern const char * const riscv_excp_names[];
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extern const char * const riscv_intr_names[];
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extern const char * const riscv_intr_names[];
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const char *riscv_cpu_get_trap_name(target_ulong cause, bool async);
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void riscv_cpu_do_interrupt(CPUState *cpu);
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void riscv_cpu_do_interrupt(CPUState *cpu);
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int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
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int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
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int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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@ -892,8 +892,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
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}
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}
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}
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}
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trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, cause < 23 ?
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trace_riscv_trap(env->mhartid, async, cause, env->pc, tval,
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(async ? riscv_intr_names : riscv_excp_names)[cause] : "(unknown)");
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riscv_cpu_get_trap_name(cause, async));
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if (env->priv <= PRV_S &&
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if (env->priv <= PRV_S &&
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cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) {
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cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) {
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