mirror of https://gitee.com/openkylin/qemu.git
linux-headers: update to 3.11
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Alexey Kardashevskiy
Paolo Bonzini
parent
4fe6e9ecb7
commit
c5daeae1b4
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@ -0,0 +1,168 @@
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/*
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* Copyright (C) 2012,2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* Derived from arch/arm/include/uapi/asm/kvm.h:
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* Copyright (C) 2012 - Virtual Open Systems and Columbia University
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* Author: Christoffer Dall <c.dall@virtualopensystems.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ARM_KVM_H__
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#define __ARM_KVM_H__
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#define KVM_SPSR_EL1 0
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#define KVM_SPSR_SVC KVM_SPSR_EL1
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#define KVM_SPSR_ABT 1
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#define KVM_SPSR_UND 2
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#define KVM_SPSR_IRQ 3
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#define KVM_SPSR_FIQ 4
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#define KVM_NR_SPSR 5
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#ifndef __ASSEMBLY__
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#include <asm/types.h>
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#include <asm/ptrace.h>
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#define __KVM_HAVE_GUEST_DEBUG
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#define __KVM_HAVE_IRQ_LINE
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#define KVM_REG_SIZE(id) \
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(1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
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struct kvm_regs {
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struct user_pt_regs regs; /* sp = sp_el0 */
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__u64 sp_el1;
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__u64 elr_el1;
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__u64 spsr[KVM_NR_SPSR];
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struct user_fpsimd_state fp_regs;
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};
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/* Supported Processor Types */
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#define KVM_ARM_TARGET_AEM_V8 0
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#define KVM_ARM_TARGET_FOUNDATION_V8 1
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#define KVM_ARM_TARGET_CORTEX_A57 2
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#define KVM_ARM_NUM_TARGETS 3
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/* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */
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#define KVM_ARM_DEVICE_TYPE_SHIFT 0
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#define KVM_ARM_DEVICE_TYPE_MASK (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT)
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#define KVM_ARM_DEVICE_ID_SHIFT 16
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#define KVM_ARM_DEVICE_ID_MASK (0xffff << KVM_ARM_DEVICE_ID_SHIFT)
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/* Supported device IDs */
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#define KVM_ARM_DEVICE_VGIC_V2 0
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/* Supported VGIC address types */
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#define KVM_VGIC_V2_ADDR_TYPE_DIST 0
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#define KVM_VGIC_V2_ADDR_TYPE_CPU 1
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#define KVM_VGIC_V2_DIST_SIZE 0x1000
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#define KVM_VGIC_V2_CPU_SIZE 0x2000
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#define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */
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#define KVM_ARM_VCPU_EL1_32BIT 1 /* CPU running a 32bit VM */
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struct kvm_vcpu_init {
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__u32 target;
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__u32 features[7];
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};
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struct kvm_sregs {
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};
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struct kvm_fpu {
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};
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struct kvm_guest_debug_arch {
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};
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struct kvm_debug_exit_arch {
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};
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struct kvm_sync_regs {
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};
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struct kvm_arch_memory_slot {
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};
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/* If you need to interpret the index values, here is the key: */
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#define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000
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#define KVM_REG_ARM_COPROC_SHIFT 16
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/* Normal registers are mapped as coprocessor 16. */
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#define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT)
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#define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / sizeof(__u32))
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/* Some registers need more space to represent values. */
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#define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT)
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#define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00
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#define KVM_REG_ARM_DEMUX_ID_SHIFT 8
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#define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT)
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#define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF
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#define KVM_REG_ARM_DEMUX_VAL_SHIFT 0
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/* AArch64 system registers */
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#define KVM_REG_ARM64_SYSREG (0x0013 << KVM_REG_ARM_COPROC_SHIFT)
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#define KVM_REG_ARM64_SYSREG_OP0_MASK 0x000000000000c000
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#define KVM_REG_ARM64_SYSREG_OP0_SHIFT 14
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#define KVM_REG_ARM64_SYSREG_OP1_MASK 0x0000000000003800
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#define KVM_REG_ARM64_SYSREG_OP1_SHIFT 11
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#define KVM_REG_ARM64_SYSREG_CRN_MASK 0x0000000000000780
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#define KVM_REG_ARM64_SYSREG_CRN_SHIFT 7
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#define KVM_REG_ARM64_SYSREG_CRM_MASK 0x0000000000000078
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#define KVM_REG_ARM64_SYSREG_CRM_SHIFT 3
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#define KVM_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007
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#define KVM_REG_ARM64_SYSREG_OP2_SHIFT 0
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/* KVM_IRQ_LINE irq field index values */
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#define KVM_ARM_IRQ_TYPE_SHIFT 24
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#define KVM_ARM_IRQ_TYPE_MASK 0xff
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#define KVM_ARM_IRQ_VCPU_SHIFT 16
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#define KVM_ARM_IRQ_VCPU_MASK 0xff
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#define KVM_ARM_IRQ_NUM_SHIFT 0
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#define KVM_ARM_IRQ_NUM_MASK 0xffff
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/* irq_type field */
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#define KVM_ARM_IRQ_TYPE_CPU 0
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#define KVM_ARM_IRQ_TYPE_SPI 1
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#define KVM_ARM_IRQ_TYPE_PPI 2
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/* out-of-kernel GIC cpu interrupt injection irq_number field */
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#define KVM_ARM_IRQ_CPU_IRQ 0
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#define KVM_ARM_IRQ_CPU_FIQ 1
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/* Highest supported SPI, from VGIC_NR_IRQS */
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#define KVM_ARM_IRQ_GIC_MAX 127
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/* PSCI interface */
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#define KVM_PSCI_FN_BASE 0x95c1ba5e
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#define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n))
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#define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0)
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#define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1)
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#define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2)
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#define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3)
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#define KVM_PSCI_RET_SUCCESS 0
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#define KVM_PSCI_RET_NI ((unsigned long)-1)
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#define KVM_PSCI_RET_INVAL ((unsigned long)-2)
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#define KVM_PSCI_RET_DENIED ((unsigned long)-3)
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#endif
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#endif /* __ARM_KVM_H__ */
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@ -0,0 +1 @@
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#include <asm-generic/kvm_para.h>
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@ -58,56 +58,53 @@ struct kvm_fpu {
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* bits[2..0] - Register 'sel' index.
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* bits[7..3] - Register 'rd' index.
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* bits[15..8] - Must be zero.
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* bits[63..16] - 1 -> CP0 registers.
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* bits[31..16] - 1 -> CP0 registers.
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* bits[51..32] - Must be zero.
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* bits[63..52] - As per linux/kvm.h
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*
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* Other sets registers may be added in the future. Each set would
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* have its own identifier in bits[63..16].
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*
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* The addr field of struct kvm_one_reg must point to an aligned
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* 64-bit wide location. For registers that are narrower than
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* 64-bits, the value is stored in the low order bits of the location,
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* and sign extended to 64-bits.
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* have its own identifier in bits[31..16].
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*
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* The registers defined in struct kvm_regs are also accessible, the
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* id values for these are below.
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*/
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#define KVM_REG_MIPS_R0 0
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#define KVM_REG_MIPS_R1 1
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#define KVM_REG_MIPS_R2 2
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#define KVM_REG_MIPS_R3 3
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#define KVM_REG_MIPS_R4 4
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#define KVM_REG_MIPS_R5 5
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#define KVM_REG_MIPS_R6 6
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#define KVM_REG_MIPS_R7 7
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#define KVM_REG_MIPS_R8 8
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#define KVM_REG_MIPS_R9 9
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#define KVM_REG_MIPS_R10 10
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#define KVM_REG_MIPS_R11 11
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#define KVM_REG_MIPS_R12 12
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#define KVM_REG_MIPS_R13 13
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#define KVM_REG_MIPS_R14 14
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#define KVM_REG_MIPS_R15 15
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#define KVM_REG_MIPS_R16 16
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#define KVM_REG_MIPS_R17 17
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#define KVM_REG_MIPS_R18 18
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#define KVM_REG_MIPS_R19 19
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#define KVM_REG_MIPS_R20 20
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#define KVM_REG_MIPS_R21 21
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#define KVM_REG_MIPS_R22 22
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#define KVM_REG_MIPS_R23 23
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#define KVM_REG_MIPS_R24 24
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#define KVM_REG_MIPS_R25 25
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#define KVM_REG_MIPS_R26 26
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#define KVM_REG_MIPS_R27 27
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#define KVM_REG_MIPS_R28 28
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#define KVM_REG_MIPS_R29 29
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#define KVM_REG_MIPS_R30 30
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#define KVM_REG_MIPS_R31 31
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#define KVM_REG_MIPS_R0 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 0)
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#define KVM_REG_MIPS_R1 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 1)
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#define KVM_REG_MIPS_R2 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 2)
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#define KVM_REG_MIPS_R3 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 3)
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#define KVM_REG_MIPS_R4 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 4)
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#define KVM_REG_MIPS_R5 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 5)
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#define KVM_REG_MIPS_R6 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 6)
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#define KVM_REG_MIPS_R7 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 7)
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#define KVM_REG_MIPS_R8 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 8)
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#define KVM_REG_MIPS_R9 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 9)
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#define KVM_REG_MIPS_R10 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 10)
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#define KVM_REG_MIPS_R11 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 11)
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#define KVM_REG_MIPS_R12 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 12)
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#define KVM_REG_MIPS_R13 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 13)
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#define KVM_REG_MIPS_R14 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 14)
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#define KVM_REG_MIPS_R15 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 15)
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#define KVM_REG_MIPS_R16 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 16)
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#define KVM_REG_MIPS_R17 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 17)
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#define KVM_REG_MIPS_R18 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 18)
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#define KVM_REG_MIPS_R19 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 19)
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#define KVM_REG_MIPS_R20 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 20)
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#define KVM_REG_MIPS_R21 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 21)
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#define KVM_REG_MIPS_R22 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 22)
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#define KVM_REG_MIPS_R23 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 23)
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#define KVM_REG_MIPS_R24 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 24)
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#define KVM_REG_MIPS_R25 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 25)
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#define KVM_REG_MIPS_R26 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 26)
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#define KVM_REG_MIPS_R27 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 27)
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#define KVM_REG_MIPS_R28 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 28)
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#define KVM_REG_MIPS_R29 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 29)
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#define KVM_REG_MIPS_R30 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 30)
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#define KVM_REG_MIPS_R31 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 31)
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#define KVM_REG_MIPS_HI 32
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#define KVM_REG_MIPS_LO 33
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#define KVM_REG_MIPS_PC 34
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#define KVM_REG_MIPS_HI (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 32)
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#define KVM_REG_MIPS_LO (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 33)
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#define KVM_REG_MIPS_PC (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 34)
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/*
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* KVM MIPS specific structures and definitions
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@ -666,6 +666,7 @@ struct kvm_ppc_smmu_info {
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#define KVM_CAP_IRQ_MPIC 90
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#define KVM_CAP_PPC_RTAS 91
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#define KVM_CAP_IRQ_XICS 92
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#define KVM_CAP_ARM_EL1_32BIT 93
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#ifdef KVM_CAP_IRQ_ROUTING
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@ -783,6 +784,8 @@ struct kvm_dirty_tlb {
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#define KVM_REG_IA64 0x3000000000000000ULL
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#define KVM_REG_ARM 0x4000000000000000ULL
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#define KVM_REG_S390 0x5000000000000000ULL
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#define KVM_REG_ARM64 0x6000000000000000ULL
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#define KVM_REG_MIPS 0x7000000000000000ULL
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#define KVM_REG_SIZE_SHIFT 52
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#define KVM_REG_SIZE_MASK 0x00f0000000000000ULL
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@ -22,6 +22,7 @@
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/* Extensions */
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#define VFIO_TYPE1_IOMMU 1
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#define VFIO_SPAPR_TCE_IOMMU 2
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/*
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* The IOCTL interface is designed for extensibility by embedding the
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@ -361,10 +362,14 @@ struct vfio_iommu_type1_dma_map {
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#define VFIO_IOMMU_MAP_DMA _IO(VFIO_TYPE, VFIO_BASE + 13)
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/**
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* VFIO_IOMMU_UNMAP_DMA - _IOW(VFIO_TYPE, VFIO_BASE + 14, struct vfio_dma_unmap)
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* VFIO_IOMMU_UNMAP_DMA - _IOWR(VFIO_TYPE, VFIO_BASE + 14,
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* struct vfio_dma_unmap)
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*
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* Unmap IO virtual addresses using the provided struct vfio_dma_unmap.
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* Caller sets argsz.
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* Caller sets argsz. The actual unmapped size is returned in the size
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* field. No guarantee is made to the user that arbitrary unmaps of iova
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* or size different from those used in the original mapping call will
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* succeed.
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*/
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struct vfio_iommu_type1_dma_unmap {
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__u32 argsz;
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@ -375,4 +380,37 @@ struct vfio_iommu_type1_dma_unmap {
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#define VFIO_IOMMU_UNMAP_DMA _IO(VFIO_TYPE, VFIO_BASE + 14)
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/*
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* IOCTLs to enable/disable IOMMU container usage.
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* No parameters are supported.
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*/
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#define VFIO_IOMMU_ENABLE _IO(VFIO_TYPE, VFIO_BASE + 15)
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#define VFIO_IOMMU_DISABLE _IO(VFIO_TYPE, VFIO_BASE + 16)
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/* -------- Additional API for SPAPR TCE (Server POWERPC) IOMMU -------- */
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/*
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* The SPAPR TCE info struct provides the information about the PCI bus
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* address ranges available for DMA, these values are programmed into
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* the hardware so the guest has to know that information.
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*
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* The DMA 32 bit window start is an absolute PCI bus address.
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* The IOVA address passed via map/unmap ioctls are absolute PCI bus
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* addresses too so the window works as a filter rather than an offset
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* for IOVA addresses.
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*
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* A flag will need to be added if other page sizes are supported,
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* so as defined here, it is always 4k.
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*/
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struct vfio_iommu_spapr_tce_info {
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__u32 argsz;
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__u32 flags; /* reserved for future use */
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__u32 dma32_window_start; /* 32 bit window start (bytes) */
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__u32 dma32_window_size; /* 32 bit window size (bytes) */
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};
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#define VFIO_IOMMU_SPAPR_TCE_GET_INFO _IO(VFIO_TYPE, VFIO_BASE + 12)
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/* ***************************************************************** */
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#endif /* VFIO_H */
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@ -51,4 +51,7 @@
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* suppressed them? */
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#define VIRTIO_F_NOTIFY_ON_EMPTY 24
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/* Can the device handle any descriptor layout? */
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#define VIRTIO_F_ANY_LAYOUT 27
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#endif /* _LINUX_VIRTIO_CONFIG_H */
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