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sun4u: convert to memory API 

fixes memory leak on repeated BAR map/unmap

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Avi Kivity 2011-08-08 16:09:22 +03:00 committed by Anthony Liguori
parent af956cadc3
commit c5e6fb7e4a
1 changed files with 23 additions and 28 deletions
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51
hw/sun4u.c
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@ -91,6 +91,12 @@ struct hwdef {
uint64_t console_serial_base; uint64_t console_serial_base;
}; };
typedef struct EbusState {
PCIDevice pci_dev;
MemoryRegion bar0;
MemoryRegion bar1;
} EbusState;
int DMA_get_channel_mode (int nchan) int DMA_get_channel_mode (int nchan)
{ {
return 0; return 0;
@ -518,21 +524,6 @@ void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit)
} }
} }
static void ebus_mmio_mapfunc(PCIDevice *pci_dev, int region_num,
pcibus_t addr, pcibus_t size, int type)
{
EBUS_DPRINTF("Mapping region %d registers at %" FMT_PCIBUS "\n",
region_num, addr);
switch (region_num) {
case 0:
isa_mmio_init(addr, 0x1000000);
break;
case 1:
isa_mmio_init(addr, 0x800000);
break;
}
}
static void dummy_isa_irq_handler(void *opaque, int n, int level) static void dummy_isa_irq_handler(void *opaque, int n, int level)
{ {
} }
@ -549,27 +540,31 @@ pci_ebus_init(PCIBus *bus, int devfn)
} }
static int static int
pci_ebus_init1(PCIDevice *s) pci_ebus_init1(PCIDevice *pci_dev)
{ {
isa_bus_new(&s->qdev); EbusState *s = DO_UPCAST(EbusState, pci_dev, pci_dev);
s->config[0x04] = 0x06; // command = bus master, pci mem isa_bus_new(&pci_dev->qdev);
s->config[0x05] = 0x00;
s->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
s->config[0x07] = 0x03; // status = medium devsel
s->config[0x09] = 0x00; // programming i/f
s->config[0x0D] = 0x0a; // latency_timer
pci_register_bar(s, 0, 0x1000000, PCI_BASE_ADDRESS_SPACE_MEMORY, pci_dev->config[0x04] = 0x06; // command = bus master, pci mem
ebus_mmio_mapfunc); pci_dev->config[0x05] = 0x00;
pci_register_bar(s, 1, 0x800000, PCI_BASE_ADDRESS_SPACE_MEMORY, pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
ebus_mmio_mapfunc); pci_dev->config[0x07] = 0x03; // status = medium devsel
pci_dev->config[0x09] = 0x00; // programming i/f
pci_dev->config[0x0D] = 0x0a; // latency_timer
isa_mmio_setup(&s->bar0, 0x1000000);
pci_register_bar_region(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY,
&s->bar0);
isa_mmio_setup(&s->bar1, 0x800000);
pci_register_bar_region(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY,
&s->bar1);
return 0; return 0;
} }
static PCIDeviceInfo ebus_info = { static PCIDeviceInfo ebus_info = {
.qdev.name = "ebus", .qdev.name = "ebus",
.qdev.size = sizeof(PCIDevice), .qdev.size = sizeof(EbusState),
.init = pci_ebus_init1, .init = pci_ebus_init1,
.vendor_id = PCI_VENDOR_ID_SUN, .vendor_id = PCI_VENDOR_ID_SUN,
.device_id = PCI_DEVICE_ID_SUN_EBUS, .device_id = PCI_DEVICE_ID_SUN_EBUS,