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tcg-aarch64: Use adrp in tcg_out_movi 

Loading an qemu pointer as an immediate happens often.  E.g.

- exit_tb $0x7fa8140013
+ exit_tb $0x7f81ee0013
...
- :  d2800260        mov     x0, #0x13
- :  f2b50280        movk    x0, #0xa814, lsl #16
- :  f2c00fe0        movk    x0, #0x7f, lsl #32
+ :  90ff1000        adrp    x0, 0x7f81ee0000
+ :  91004c00        add     x0, x0, #0x13

Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson 2013-08-10 15:28:48 -04:00 committed by Richard Henderson
parent d8918df577
commit c6e310d938
1 changed files with 23 additions and 0 deletions
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23
tcg/aarch64/tcg-target.c
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@ -294,6 +294,10 @@ typedef enum {
I3405_MOVZ = 0x52800000, I3405_MOVZ = 0x52800000,
I3405_MOVK = 0x72800000, I3405_MOVK = 0x72800000,
/* PC relative addressing instructions. */
I3406_ADR = 0x10000000,
I3406_ADRP = 0x90000000,
/* Add/subtract shifted register instructions (without a shift). */ /* Add/subtract shifted register instructions (without a shift). */
I3502_ADD = 0x0b000000, I3502_ADD = 0x0b000000,
I3502_ADDS = 0x2b000000, I3502_ADDS = 0x2b000000,
@ -457,6 +461,12 @@ static void tcg_out_insn_3405(TCGContext *s, AArch64Insn insn, TCGType ext,
tcg_out32(s, insn | ext << 31 | shift << (21 - 4) | half << 5 | rd); tcg_out32(s, insn | ext << 31 | shift << (21 - 4) | half << 5 | rd);
} }
static void tcg_out_insn_3406(TCGContext *s, AArch64Insn insn,
TCGReg rd, int64_t disp)
{
tcg_out32(s, insn | (disp & 3) << 29 | (disp & 0x1ffffc) << (5 - 2) | rd);
}
/* This function is for both 3.5.2 (Add/Subtract shifted register), for /* This function is for both 3.5.2 (Add/Subtract shifted register), for
the rare occasion when we actually want to supply a shift amount. */ the rare occasion when we actually want to supply a shift amount. */
static inline void tcg_out_insn_3502S(TCGContext *s, AArch64Insn insn, static inline void tcg_out_insn_3502S(TCGContext *s, AArch64Insn insn,
@ -596,6 +606,19 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
return; return;
} }
/* Look for host pointer values within 4G of the PC. This happens
often when loading pointers to QEMU's own data structures. */
if (type == TCG_TYPE_I64) {
tcg_target_long disp = (value >> 12) - ((intptr_t)s->code_ptr >> 12);
if (disp == sextract64(disp, 0, 21)) {
tcg_out_insn(s, 3406, ADRP, rd, disp);
if (value & 0xfff) {
tcg_out_insn(s, 3401, ADDI, type, rd, rd, value & 0xfff);
}
return;
}
}
/* Would it take fewer insns to begin with MOVN? For the value and its /* Would it take fewer insns to begin with MOVN? For the value and its
inverse, count the number of 16-bit lanes that are 0. */ inverse, count the number of 16-bit lanes that are 0. */
for (i = wantinv = imask = 0; i < 64; i += 16) { for (i = wantinv = imask = 0; i < 64; i += 16) {