mirror of https://gitee.com/openkylin/qemu.git
hw/block/nvme: indicate CMB support through controller capabilities register
This patch sets CMBS bit in controller capabilities register when user configures NVMe driver with CMB support, so capabilites are correctly reported to guest OS. Signed-off-by: Andrzej Jakowski <andrzej.jakowski@linux.intel.com> Reviewed-by: Maxim Levitsky <mlevitsky@gmail.com> Reviewed-by: Minwoo Im <minwoo.im.dev@gmail.com> Reviewed-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
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@ -4374,6 +4374,7 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev)
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NVME_CAP_SET_CSS(n->bar.cap, NVME_CAP_CSS_CSI_SUPP);
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NVME_CAP_SET_CSS(n->bar.cap, NVME_CAP_CSS_ADMIN_ONLY);
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NVME_CAP_SET_MPSMAX(n->bar.cap, 4);
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NVME_CAP_SET_CMBS(n->bar.cap, n->params.cmb_size_mb ? 1 : 0);
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n->bar.vs = NVME_SPEC_VER;
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n->bar.intmc = n->bar.intms = 0;
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@ -36,6 +36,7 @@ enum NvmeCapShift {
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CAP_MPSMIN_SHIFT = 48,
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CAP_MPSMAX_SHIFT = 52,
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CAP_PMR_SHIFT = 56,
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CAP_CMB_SHIFT = 57,
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};
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enum NvmeCapMask {
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@ -49,6 +50,7 @@ enum NvmeCapMask {
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CAP_MPSMIN_MASK = 0xf,
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CAP_MPSMAX_MASK = 0xf,
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CAP_PMR_MASK = 0x1,
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CAP_CMB_MASK = 0x1,
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};
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#define NVME_CAP_MQES(cap) (((cap) >> CAP_MQES_SHIFT) & CAP_MQES_MASK)
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@ -79,9 +81,11 @@ enum NvmeCapMask {
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#define NVME_CAP_SET_MPSMIN(cap, val) (cap |= (uint64_t)(val & CAP_MPSMIN_MASK)\
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<< CAP_MPSMIN_SHIFT)
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#define NVME_CAP_SET_MPSMAX(cap, val) (cap |= (uint64_t)(val & CAP_MPSMAX_MASK)\
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<< CAP_MPSMAX_SHIFT)
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#define NVME_CAP_SET_PMRS(cap, val) (cap |= (uint64_t)(val & CAP_PMR_MASK)\
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<< CAP_PMR_SHIFT)
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<< CAP_MPSMAX_SHIFT)
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#define NVME_CAP_SET_PMRS(cap, val) (cap |= (uint64_t)(val & CAP_PMR_MASK) \
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<< CAP_PMR_SHIFT)
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#define NVME_CAP_SET_CMBS(cap, val) (cap |= (uint64_t)(val & CAP_CMB_MASK) \
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<< CAP_CMB_SHIFT)
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enum NvmeCapCss {
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NVME_CAP_CSS_NVM = 1 << 0,
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