mirror of https://gitee.com/openkylin/qemu.git
tcg/s390: Split out target constraints to tcg-target-con-str.h
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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/* SPDX-License-Identifier: MIT */
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/*
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* Define S390 target-specific operand constraints.
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* Copyright (c) 2021 Linaro
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*/
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/*
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* Define constraint letters for register sets:
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* REGS(letter, register_mask)
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*/
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REGS('r', ALL_GENERAL_REGS)
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REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS)
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/*
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* A (single) even/odd pair for division.
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* TODO: Add something to the register allocator to allow
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* this kind of regno+1 pairing to be done more generally.
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*/
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REGS('a', 1u << TCG_REG_R2)
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REGS('b', 1u << TCG_REG_R3)
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/*
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* Define constraint letters for constants:
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* CONST(letter, TCG_CT_CONST_* bit set)
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*/
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CONST('A', TCG_CT_CONST_S33)
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CONST('I', TCG_CT_CONST_S16)
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CONST('J', TCG_CT_CONST_S32)
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CONST('Z', TCG_CT_CONST_ZERO)
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@ -42,6 +42,19 @@
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#define TCG_CT_CONST_S33 0x400
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#define TCG_CT_CONST_ZERO 0x800
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#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 16)
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/*
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* For softmmu, we need to avoid conflicts with the first 3
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* argument registers to perform the tlb lookup, and to call
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* the helper function.
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*/
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#ifdef CONFIG_SOFTMMU
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#define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_R2, 3)
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#else
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#define SOFTMMU_RESERVE_REGS 0
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#endif
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/* Several places within the instruction set 0 means "no register"
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rather than TCG_REG_R0. */
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#define TCG_REG_NONE 0
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@ -403,46 +416,6 @@ static bool patch_reloc(tcg_insn_unit *src_rw, int type,
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return false;
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}
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/* parse target specific constraints */
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static const char *target_parse_constraint(TCGArgConstraint *ct,
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const char *ct_str, TCGType type)
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{
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switch (*ct_str++) {
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case 'r': /* all registers */
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ct->regs = 0xffff;
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break;
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case 'L': /* qemu_ld/st constraint */
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ct->regs = 0xffff;
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tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
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tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
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tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
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break;
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case 'a': /* force R2 for division */
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ct->regs = 0;
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tcg_regset_set_reg(ct->regs, TCG_REG_R2);
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break;
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case 'b': /* force R3 for division */
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ct->regs = 0;
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tcg_regset_set_reg(ct->regs, TCG_REG_R3);
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break;
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case 'A':
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ct->ct |= TCG_CT_CONST_S33;
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break;
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case 'I':
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ct->ct |= TCG_CT_CONST_S16;
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break;
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case 'J':
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ct->ct |= TCG_CT_CONST_S32;
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break;
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case 'Z':
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ct->ct |= TCG_CT_CONST_ZERO;
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break;
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default:
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return NULL;
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}
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return ct_str;
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}
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/* Test if a constant matches the constraint. */
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static int tcg_target_const_match(tcg_target_long val, TCGType type,
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const TCGArgConstraint *arg_ct)
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@ -159,5 +159,6 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
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#define TCG_TARGET_NEED_LDST_LABELS
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#endif
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#define TCG_TARGET_NEED_POOL_LABELS
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#define TCG_TARGET_CON_STR_H
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#endif
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