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target/arm: Convert Neon VHADD 3-reg-same insns 

Convert the Neon VHADD insns in the 3-reg-same group to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200512163904.10918-5-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2020-05-12 17:38:51 +01:00
parent 35d4352fa9
commit cb294bca86
3 changed files with 27 additions and 3 deletions
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2
target/arm/neon-dp.decode
View File

@ -42,6 +42,8 @@
@3same .... ... . . . size:2 .... .... .... . q:1 . . .... \ @3same .... ... . . . size:2 .... .... .... . q:1 . . .... \
&3same vm=%vm_dp vn=%vn_dp vd=%vd_dp &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp
VHADD_S_3s 1111 001 0 0 . .. .... .... 0000 . . . 0 .... @3same
VHADD_U_3s 1111 001 1 0 . .. .... .... 0000 . . . 0 .... @3same
VQADD_S_3s 1111 001 0 0 . .. .... .... 0000 . . . 1 .... @3same VQADD_S_3s 1111 001 0 0 . .. .... .... 0000 . . . 1 .... @3same
VQADD_U_3s 1111 001 1 0 . .. .... .... 0000 . . . 1 .... @3same VQADD_U_3s 1111 001 1 0 . .. .... .... 0000 . . . 1 .... @3same

24
target/arm/translate-neon.inc.c
View File

@ -849,3 +849,27 @@ DO_3SAME_64_ENV(VQSHL_S64, gen_helper_neon_qshl_s64)
DO_3SAME_64_ENV(VQSHL_U64, gen_helper_neon_qshl_u64) DO_3SAME_64_ENV(VQSHL_U64, gen_helper_neon_qshl_u64)
DO_3SAME_64_ENV(VQRSHL_S64, gen_helper_neon_qrshl_s64) DO_3SAME_64_ENV(VQRSHL_S64, gen_helper_neon_qrshl_s64)
DO_3SAME_64_ENV(VQRSHL_U64, gen_helper_neon_qrshl_u64) DO_3SAME_64_ENV(VQRSHL_U64, gen_helper_neon_qrshl_u64)
#define DO_3SAME_32(INSN, FUNC) \
static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \
uint32_t rn_ofs, uint32_t rm_ofs, \
uint32_t oprsz, uint32_t maxsz) \
{ \
static const GVecGen3 ops[4] = { \
{ .fni4 = gen_helper_neon_##FUNC##8 }, \
{ .fni4 = gen_helper_neon_##FUNC##16 }, \
{ .fni4 = gen_helper_neon_##FUNC##32 }, \
{ 0 }, \
}; \
tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &ops[vece]); \
} \
static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \
{ \
if (a->size > 2) { \
return false; \
} \
return do_3same(s, a, gen_##INSN##_3s); \
}
DO_3SAME_32(VHADD_S, hadd_s)
DO_3SAME_32(VHADD_U, hadd_u)

4
target/arm/translate.c
View File

@ -5454,6 +5454,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
case NEON_3R_VML: case NEON_3R_VML:
case NEON_3R_VSHL: case NEON_3R_VSHL:
case NEON_3R_SHA: case NEON_3R_SHA:
case NEON_3R_VHADD:
/* Already handled by decodetree */ /* Already handled by decodetree */
return 1; return 1;
} }
@ -5534,9 +5535,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
tmp2 = neon_load_reg(rm, pass); tmp2 = neon_load_reg(rm, pass);
} }
switch (op) { switch (op) {
case NEON_3R_VHADD:
GEN_NEON_INTEGER_OP(hadd);
break;
case NEON_3R_VRHADD: case NEON_3R_VRHADD:
GEN_NEON_INTEGER_OP(rhadd); GEN_NEON_INTEGER_OP(rhadd);
break; break;