mirror of https://gitee.com/openkylin/qemu.git
target/arm: Update get_a64_user_mem_index for VHE
The EL2&0 translation regime is affected by Load Register (unpriv). The code structure used here will facilitate later changes in this area for implementing UAO and NV. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200206105448.4726-36-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -3214,10 +3214,10 @@ typedef ARMCPU ArchCPU;
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* | | | TBFLAG_A32 | |
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* | | +-----+----------+ TBFLAG_AM32 |
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* | TBFLAG_ANY | |TBFLAG_M32| |
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* | | +-------------------------|
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* | | | TBFLAG_A64 |
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* +--------------+-----------+-------------------------+
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* 31 20 14 0
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* | | +-+----------+--------------|
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* | | | TBFLAG_A64 |
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* +--------------+---------+---------------------------+
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* 31 20 15 0
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*
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* Unless otherwise noted, these bits are cached in env->hflags.
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*/
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@ -3283,6 +3283,7 @@ FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1)
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FIELD(TBFLAG_A64, BT, 9, 1)
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FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */
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FIELD(TBFLAG_A64, TBID, 12, 2)
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FIELD(TBFLAG_A64, UNPRIV, 14, 1)
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static inline bool bswap_code(bool sctlr_b)
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{
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@ -12011,6 +12011,28 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
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}
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}
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/* Compute the condition for using AccType_UNPRIV for LDTR et al. */
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/* TODO: ARMv8.2-UAO */
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switch (mmu_idx) {
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case ARMMMUIdx_E10_1:
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case ARMMMUIdx_SE10_1:
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/* TODO: ARMv8.3-NV */
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flags = FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1);
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break;
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case ARMMMUIdx_E20_2:
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/* TODO: ARMv8.4-SecEL2 */
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/*
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* Note that E20_2 is gated by HCR_EL2.E2H == 1, but E20_0 is
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* gated by HCR_EL2.<E2H,TGE> == '11', and so is LDTR.
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*/
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if (env->cp15.hcr_el2 & HCR_TGE) {
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flags = FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1);
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}
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break;
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default:
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break;
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}
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return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
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}
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@ -105,25 +105,36 @@ void a64_translate_init(void)
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offsetof(CPUARMState, exclusive_high), "exclusive_high");
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}
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static inline int get_a64_user_mem_index(DisasContext *s)
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/*
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* Return the core mmu_idx to use for A64 "unprivileged load/store" insns
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*/
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static int get_a64_user_mem_index(DisasContext *s)
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{
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/* Return the core mmu_idx to use for A64 "unprivileged load/store" insns:
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* if EL1, access as if EL0; otherwise access at current EL
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/*
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* If AccType_UNPRIV is not used, the insn uses AccType_NORMAL,
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* which is the usual mmu_idx for this cpu state.
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*/
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ARMMMUIdx useridx;
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ARMMMUIdx useridx = s->mmu_idx;
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switch (s->mmu_idx) {
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case ARMMMUIdx_E10_1:
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useridx = ARMMMUIdx_E10_0;
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break;
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case ARMMMUIdx_SE10_1:
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useridx = ARMMMUIdx_SE10_0;
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break;
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case ARMMMUIdx_Stage2:
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g_assert_not_reached();
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default:
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useridx = s->mmu_idx;
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break;
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if (s->unpriv) {
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/*
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* We have pre-computed the condition for AccType_UNPRIV.
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* Therefore we should never get here with a mmu_idx for
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* which we do not know the corresponding user mmu_idx.
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*/
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switch (useridx) {
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case ARMMMUIdx_E10_1:
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useridx = ARMMMUIdx_E10_0;
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break;
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case ARMMMUIdx_E20_2:
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useridx = ARMMMUIdx_E20_0;
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break;
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case ARMMMUIdx_SE10_1:
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useridx = ARMMMUIdx_SE10_0;
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break;
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default:
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g_assert_not_reached();
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}
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}
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return arm_to_core_mmu_idx(useridx);
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}
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@ -14171,6 +14182,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
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dc->pauth_active = FIELD_EX32(tb_flags, TBFLAG_A64, PAUTH_ACTIVE);
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dc->bt = FIELD_EX32(tb_flags, TBFLAG_A64, BT);
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dc->btype = FIELD_EX32(tb_flags, TBFLAG_A64, BTYPE);
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dc->unpriv = FIELD_EX32(tb_flags, TBFLAG_A64, UNPRIV);
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dc->vec_len = 0;
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dc->vec_stride = 0;
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dc->cp_regs = arm_cpu->cp_regs;
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@ -73,6 +73,8 @@ typedef struct DisasContext {
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* ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*.
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*/
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bool is_ldex;
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/* True if AccType_UNPRIV should be used for LDTR et al */
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bool unpriv;
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/* True if v8.3-PAuth is active. */
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bool pauth_active;
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/* True with v8.5-BTI and SCTLR_ELx.BT* set. */
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