mirror of https://gitee.com/openkylin/qemu.git
target/riscv: Use {get,dest}_gpr for RVA
Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210823195529.560295-20-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -18,11 +18,10 @@
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* this program. If not, see <http://www.gnu.org/licenses/>.
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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*/
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static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
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static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
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{
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{
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TCGv src1 = tcg_temp_new();
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TCGv src1 = get_gpr(ctx, a->rs1, EXT_ZERO);
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/* Put addr in load_res, data in load_val. */
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gen_get_gpr(ctx, src1, a->rs1);
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if (a->rl) {
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if (a->rl) {
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tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
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tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
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}
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}
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@ -30,33 +29,33 @@ static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
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if (a->aq) {
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if (a->aq) {
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tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
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tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
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}
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}
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/* Put addr in load_res, data in load_val. */
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tcg_gen_mov_tl(load_res, src1);
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tcg_gen_mov_tl(load_res, src1);
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gen_set_gpr(ctx, a->rd, load_val);
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gen_set_gpr(ctx, a->rd, load_val);
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tcg_temp_free(src1);
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return true;
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return true;
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}
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}
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static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
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static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
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{
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{
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TCGv src1 = tcg_temp_new();
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TCGv dest, src1, src2;
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TCGv src2 = tcg_temp_new();
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TCGv dat = tcg_temp_new();
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TCGLabel *l1 = gen_new_label();
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TCGLabel *l1 = gen_new_label();
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TCGLabel *l2 = gen_new_label();
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TCGLabel *l2 = gen_new_label();
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gen_get_gpr(ctx, src1, a->rs1);
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src1 = get_gpr(ctx, a->rs1, EXT_ZERO);
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tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
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tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
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gen_get_gpr(ctx, src2, a->rs2);
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/*
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/*
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* Note that the TCG atomic primitives are SC,
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* Note that the TCG atomic primitives are SC,
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* so we can ignore AQ/RL along this path.
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* so we can ignore AQ/RL along this path.
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*/
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*/
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tcg_gen_atomic_cmpxchg_tl(src1, load_res, load_val, src2,
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dest = dest_gpr(ctx, a->rd);
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src2 = get_gpr(ctx, a->rs2, EXT_NONE);
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tcg_gen_atomic_cmpxchg_tl(dest, load_res, load_val, src2,
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ctx->mem_idx, mop);
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ctx->mem_idx, mop);
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tcg_gen_setcond_tl(TCG_COND_NE, dat, src1, load_val);
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tcg_gen_setcond_tl(TCG_COND_NE, dest, dest, load_val);
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gen_set_gpr(ctx, a->rd, dat);
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gen_set_gpr(ctx, a->rd, dest);
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tcg_gen_br(l2);
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tcg_gen_br(l2);
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gen_set_label(l1);
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gen_set_label(l1);
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@ -65,8 +64,7 @@ static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
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* provide the memory barrier implied by AQ/RL.
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* provide the memory barrier implied by AQ/RL.
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*/
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*/
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tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + a->rl * TCG_BAR_STRL);
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tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + a->rl * TCG_BAR_STRL);
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tcg_gen_movi_tl(dat, 1);
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gen_set_gpr(ctx, a->rd, tcg_constant_tl(1));
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gen_set_gpr(ctx, a->rd, dat);
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gen_set_label(l2);
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gen_set_label(l2);
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/*
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/*
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@ -75,9 +73,6 @@ static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
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*/
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*/
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tcg_gen_movi_tl(load_res, -1);
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tcg_gen_movi_tl(load_res, -1);
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tcg_temp_free(dat);
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tcg_temp_free(src1);
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tcg_temp_free(src2);
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return true;
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return true;
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}
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}
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@ -85,17 +80,13 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a,
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void(*func)(TCGv, TCGv, TCGv, TCGArg, MemOp),
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void(*func)(TCGv, TCGv, TCGv, TCGArg, MemOp),
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MemOp mop)
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MemOp mop)
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{
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{
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TCGv src1 = tcg_temp_new();
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TCGv dest = dest_gpr(ctx, a->rd);
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TCGv src2 = tcg_temp_new();
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TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
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TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
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gen_get_gpr(ctx, src1, a->rs1);
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func(dest, src1, src2, ctx->mem_idx, mop);
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gen_get_gpr(ctx, src2, a->rs2);
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(*func)(src2, src1, src2, ctx->mem_idx, mop);
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gen_set_gpr(ctx, a->rd, dest);
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gen_set_gpr(ctx, a->rd, src2);
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tcg_temp_free(src1);
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tcg_temp_free(src2);
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return true;
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return true;
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}
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}
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