mirror of https://gitee.com/openkylin/qemu.git
ds1225y: convert to qdev device, and use it in MIPS Jazz emulation
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
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d43ed9ec25
commit
cd3e2409a3
106
hw/ds1225y.c
106
hw/ds1225y.c
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@ -22,21 +22,20 @@
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* THE SOFTWARE.
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* THE SOFTWARE.
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*/
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*/
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#include "hw.h"
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#include "sysbus.h"
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#include "mips.h"
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#include "trace.h"
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#include "trace.h"
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typedef struct ds1225y_t
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typedef struct {
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{
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DeviceState qdev;
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uint32_t chip_size;
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uint32_t chip_size;
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char *filename;
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QEMUFile *file;
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QEMUFile *file;
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uint8_t *contents;
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uint8_t *contents;
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} ds1225y_t;
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} NvRamState;
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static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
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static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
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{
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{
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ds1225y_t *s = opaque;
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NvRamState *s = opaque;
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uint32_t val;
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uint32_t val;
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val = s->contents[addr];
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val = s->contents[addr];
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@ -64,7 +63,7 @@ static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
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static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
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static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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{
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ds1225y_t *s = opaque;
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NvRamState *s = opaque;
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val &= 0xff;
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val &= 0xff;
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trace_nvram_write(addr, s->contents[addr], val);
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trace_nvram_write(addr, s->contents[addr], val);
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@ -103,34 +102,83 @@ static CPUWriteMemoryFunc * const nvram_write[] = {
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&nvram_writel,
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&nvram_writel,
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};
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};
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/* Initialisation routine */
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static int nvram_post_load(void *opaque, int version_id)
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void *ds1225y_init(target_phys_addr_t mem_base, const char *filename)
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{
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{
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ds1225y_t *s;
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NvRamState *s = opaque;
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int mem_indexRW;
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QEMUFile *file;
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s = qemu_mallocz(sizeof(ds1225y_t));
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/* Close file, as filename may has changed in load/store process */
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s->chip_size = 0x2000; /* Fixed for ds1225y chip: 8 KiB */
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if (s->file) {
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s->contents = qemu_mallocz(s->chip_size);
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qemu_fclose(s->file);
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/* Read current file */
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file = qemu_fopen(filename, "rb");
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if (file) {
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/* Read nvram contents */
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qemu_get_buffer(file, s->contents, s->chip_size);
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qemu_fclose(file);
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}
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}
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s->file = qemu_fopen(filename, "wb");
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/* Write back nvram contents */
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s->file = qemu_fopen(s->filename, "wb");
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if (s->file) {
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if (s->file) {
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/* Write back contents, as 'wb' mode cleaned the file */
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/* Write back contents, as 'wb' mode cleaned the file */
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qemu_put_buffer(s->file, s->contents, s->chip_size);
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qemu_put_buffer(s->file, s->contents, s->chip_size);
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qemu_fflush(s->file);
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qemu_fflush(s->file);
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}
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}
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/* Read/write memory */
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return 0;
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mem_indexRW = cpu_register_io_memory(nvram_read, nvram_write, s,
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DEVICE_NATIVE_ENDIAN);
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cpu_register_physical_memory(mem_base, s->chip_size, mem_indexRW);
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return s;
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}
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}
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static const VMStateDescription vmstate_nvram = {
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.name = "nvram",
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.version_id = 0,
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.minimum_version_id = 0,
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.minimum_version_id_old = 0,
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.post_load = nvram_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_VARRAY_UINT32(contents, NvRamState, chip_size, 0,
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vmstate_info_uint8, uint8_t),
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VMSTATE_END_OF_LIST()
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}
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};
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typedef struct {
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SysBusDevice busdev;
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NvRamState nvram;
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} SysBusNvRamState;
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static int nvram_sysbus_initfn(SysBusDevice *dev)
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{
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NvRamState *s = &FROM_SYSBUS(SysBusNvRamState, dev)->nvram;
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QEMUFile *file;
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int s_io;
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s->contents = qemu_mallocz(s->chip_size);
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s_io = cpu_register_io_memory(nvram_read, nvram_write, s,
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DEVICE_NATIVE_ENDIAN);
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sysbus_init_mmio(dev, s->chip_size, s_io);
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/* Read current file */
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file = qemu_fopen(s->filename, "rb");
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if (file) {
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/* Read nvram contents */
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qemu_get_buffer(file, s->contents, s->chip_size);
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qemu_fclose(file);
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}
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nvram_post_load(s, 0);
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return 0;
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}
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static SysBusDeviceInfo nvram_sysbus_info = {
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.qdev.name = "ds1225y",
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.qdev.size = sizeof(SysBusNvRamState),
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.qdev.vmsd = &vmstate_nvram,
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.init = nvram_sysbus_initfn,
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.qdev.props = (Property[]) {
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DEFINE_PROP_UINT32("size", SysBusNvRamState, nvram.chip_size, 0x2000),
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DEFINE_PROP_STRING("filename", SysBusNvRamState, nvram.filename),
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DEFINE_PROP_END_OF_LIST(),
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},
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};
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static void nvram_register(void)
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{
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sysbus_register_withprop(&nvram_sysbus_info);
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}
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device_init(nvram_register)
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@ -8,9 +8,6 @@ PCIBus *gt64120_register(qemu_irq *pic);
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/* bonito.c */
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/* bonito.c */
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PCIBus *bonito_init(qemu_irq *pic);
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PCIBus *bonito_init(qemu_irq *pic);
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/* ds1225y.c */
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void *ds1225y_init(target_phys_addr_t mem_base, const char *filename);
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/* g364fb.c */
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/* g364fb.c */
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int g364fb_mm_init(target_phys_addr_t vram_base,
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int g364fb_mm_init(target_phys_addr_t vram_base,
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target_phys_addr_t ctrl_base, int it_shift,
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target_phys_addr_t ctrl_base, int it_shift,
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@ -37,6 +37,7 @@
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#include "loader.h"
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#include "loader.h"
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#include "mc146818rtc.h"
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#include "mc146818rtc.h"
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#include "blockdev.h"
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#include "blockdev.h"
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#include "sysbus.h"
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enum jazz_model_e
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enum jazz_model_e
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{
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{
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@ -115,6 +116,8 @@ void mips_jazz_init (ram_addr_t ram_size,
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void* rc4030_opaque;
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void* rc4030_opaque;
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int s_rtc, s_dma_dummy;
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int s_rtc, s_dma_dummy;
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NICInfo *nd;
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NICInfo *nd;
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DeviceState *dev;
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SysBusDevice *sysbus;
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ISADevice *pit;
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ISADevice *pit;
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DriveInfo *fds[MAX_FD];
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DriveInfo *fds[MAX_FD];
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qemu_irq esp_reset, dma_enable;
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qemu_irq esp_reset, dma_enable;
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@ -266,8 +269,11 @@ void mips_jazz_init (ram_addr_t ram_size,
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/* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
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/* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
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audio_init(i8259, NULL);
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audio_init(i8259, NULL);
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/* NVRAM: Unprotected at 0x9000, Protected at 0xa000, Read only at 0xb000 */
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/* NVRAM */
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ds1225y_init(0x80009000, "nvram");
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dev = qdev_create(NULL, "ds1225y");
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qdev_init_nofail(dev);
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sysbus = sysbus_from_qdev(dev);
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sysbus_mmio_map(sysbus, 0, 0x80009000);
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/* LED indicator */
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/* LED indicator */
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jazz_led_init(0x8000f000);
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jazz_led_init(0x8000f000);
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