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ppc/pnv: fix logging primitives using Ox 

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20190306085032.15744-12-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Cédric Le Goater 2019-03-06 09:50:16 +01:00 committed by David Gibson
parent 4836b45510
commit cdbaf8cd9a
2 changed files with 7 additions and 7 deletions
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10
hw/ppc/pnv_lpc.c
View File

@ -294,7 +294,7 @@ static uint64_t lpc_hc_read(void *opaque, hwaddr addr, unsigned size)
val = lpc->lpc_hc_error_addr;
break;
default:
qemu_log_mask(LOG_UNIMP, "LPC HC Unimplemented register: Ox%"
qemu_log_mask(LOG_UNIMP, "LPC HC Unimplemented register: 0x%"
HWADDR_PRIx "\n", addr);
}
return val;
@ -332,7 +332,7 @@ static void lpc_hc_write(void *opaque, hwaddr addr, uint64_t val,
case LPC_HC_ERROR_ADDRESS:
break;
default:
qemu_log_mask(LOG_UNIMP, "LPC HC Unimplemented register: Ox%"
qemu_log_mask(LOG_UNIMP, "LPC HC Unimplemented register: 0x%"
HWADDR_PRIx "\n", addr);
}
}
@ -370,7 +370,7 @@ static uint64_t opb_master_read(void *opaque, hwaddr addr, unsigned size)
val = lpc->opb_irq_input;
break;
default:
qemu_log_mask(LOG_UNIMP, "OPB MASTER Unimplemented register: Ox%"
qemu_log_mask(LOG_UNIMP, "OPBM: read on unimplemented register: 0x%"
HWADDR_PRIx "\n", addr);
}
@ -399,8 +399,8 @@ static void opb_master_write(void *opaque, hwaddr addr,
/* Read only */
break;
default:
qemu_log_mask(LOG_UNIMP, "OPB MASTER Unimplemented register: Ox%"
HWADDR_PRIx "\n", addr);
qemu_log_mask(LOG_UNIMP, "OPBM: write on unimplemented register: 0x%"
HWADDR_PRIx " val=0x%08"PRIx64"\n", addr, val);
}
}

4
hw/ppc/pnv_psi.c
View File

@ -323,7 +323,7 @@ static uint64_t pnv_psi_reg_read(PnvPsi *psi, uint32_t offset, bool mmio)
val = psi->regs[offset];
break;
default:
qemu_log_mask(LOG_UNIMP, "PSI: read at Ox%" PRIx32 "\n", offset);
qemu_log_mask(LOG_UNIMP, "PSI: read at 0x%" PRIx32 "\n", offset);
}
return val;
}
@ -382,7 +382,7 @@ static void pnv_psi_reg_write(PnvPsi *psi, uint32_t offset, uint64_t val,
pnv_psi_set_irsn(psi, val);
break;
default:
qemu_log_mask(LOG_UNIMP, "PSI: write at Ox%" PRIx32 "\n", offset);
qemu_log_mask(LOG_UNIMP, "PSI: write at 0x%" PRIx32 "\n", offset);
}
}