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Merge remote-tracking branch 'bonzini/iommu-for-anthony' into staging 

# By Paolo Bonzini
# Via Paolo Bonzini
* bonzini/iommu-for-anthony: (22 commits)
  memory: add return value to address_space_rw/read/write
  memory: propagate errors on I/O dispatch
  exec: just use io_mem_read/io_mem_write for 8-byte I/O accesses
  memory: correctly handle endian-swapped 64-bit accesses
  memory: split accesses even when the old MMIO callbacks are used
  memory: add big endian support to access_with_adjusted_size
  memory: accept mismatching sizes in memory_region_access_valid
  memory: add address_space_access_valid
  exec: implement .valid.accepts for subpages
  memory: export memory_region_access_valid to exec.c
  exec: introduce memory_access_size
  exec: introduce memory_access_is_direct
  exec: expect mr->ops to be initialized for ROM
  memory: assign MemoryRegionOps to all regions
  memory: move unassigned_mem_ops to memory.c
  memory: add address_space_translate
  memory: dispatch unassigned accesses based on .valid.accepts
  exec: do not use error_mem_read
  exec: make io_mem_unassigned private
  cputlb: simplify tlb_set_page
  ...

Message-id: 1369947836-2638-1-git-send-email-pbonzini@redhat.com
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Anthony Liguori 2013-05-31 11:32:25 -05:00
parent fd21faadb1 fd8aaa767a
commit cdf79b6454
12 changed files with 430 additions and 380 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

31
cputlb.c
View File

@ -248,13 +248,18 @@ void tlb_set_page(CPUArchState *env, target_ulong vaddr,
target_ulong code_address;
uintptr_t addend;
CPUTLBEntry *te;
hwaddr iotlb;
hwaddr iotlb, xlat, sz;
assert(size >= TARGET_PAGE_SIZE);
if (size != TARGET_PAGE_SIZE) {
tlb_add_large_page(env, vaddr, size);
}
section = phys_page_find(address_space_memory.dispatch, paddr >> TARGET_PAGE_BITS);
sz = size;
section = address_space_translate(&address_space_memory, paddr, &xlat, &sz,
false);
assert(sz >= TARGET_PAGE_SIZE);
#if defined(DEBUG_TLB)
printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx
" prot=%x idx=%d pd=0x%08lx\n",
@ -262,22 +267,18 @@ void tlb_set_page(CPUArchState *env, target_ulong vaddr,
#endif
address = vaddr;
if (!(memory_region_is_ram(section->mr) ||
memory_region_is_romd(section->mr))) {
/* IO memory case (romd handled later) */
if (!memory_region_is_ram(section->mr) && !memory_region_is_romd(section->mr)) {
/* IO memory case */
address |= TLB_MMIO;
}
if (memory_region_is_ram(section->mr) ||
memory_region_is_romd(section->mr)) {
addend = (uintptr_t)memory_region_get_ram_ptr(section->mr)
+ memory_region_section_addr(section, paddr);
} else {
addend = 0;
} else {
/* TLB_MMIO for rom/romd handled below */
addend = (uintptr_t)memory_region_get_ram_ptr(section->mr) + xlat;
}
code_address = address;
iotlb = memory_region_section_get_iotlb(env, section, vaddr, paddr, prot,
&address);
iotlb = memory_region_section_get_iotlb(env, section, vaddr, paddr, xlat,
prot, &address);
index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
env->iotlb[mmu_idx][index] = iotlb - vaddr;
@ -300,9 +301,7 @@ void tlb_set_page(CPUArchState *env, target_ulong vaddr,
/* Write access calls the I/O callback. */
te->addr_write = address | TLB_MMIO;
} else if (memory_region_is_ram(section->mr)
&& !cpu_physical_memory_is_dirty(
section->mr->ram_addr
+ memory_region_section_addr(section, paddr))) {
&& !cpu_physical_memory_is_dirty(section->mr->ram_addr + xlat)) {
te->addr_write = address | TLB_NOTDIRTY;
} else {
te->addr_write = address;

5
dma-helpers.c
View File

@ -298,6 +298,11 @@ bool iommu_dma_memory_valid(DMAContext *dma, dma_addr_t addr, dma_addr_t len,
plen = len;
}
if (!address_space_access_valid(dma->as, paddr, len,
dir == DMA_DIRECTION_FROM_DEVICE)) {
return false;
}
len -= plen;
addr += plen;
}

415
exec.c
View File

@ -50,7 +50,6 @@
#include "exec/memory-internal.h"
//#define DEBUG_UNASSIGNED
//#define DEBUG_SUBPAGE
#if !defined(CONFIG_USER_ONLY)
@ -66,8 +65,8 @@ AddressSpace address_space_io;
AddressSpace address_space_memory;
DMAContext dma_context_memory;
MemoryRegion io_mem_ram, io_mem_rom, io_mem_unassigned, io_mem_notdirty;
static MemoryRegion io_mem_subpage_ram;
MemoryRegion io_mem_rom, io_mem_notdirty;
static MemoryRegion io_mem_unassigned, io_mem_subpage_ram;
#endif
@ -182,7 +181,7 @@ static void phys_page_set(AddressSpaceDispatch *d,
phys_page_set_level(&d->phys_map, &index, &nb, leaf, P_L2_LEVELS - 1);
}
MemoryRegionSection *phys_page_find(AddressSpaceDispatch *d, hwaddr index)
static MemoryRegionSection *phys_page_find(AddressSpaceDispatch *d, hwaddr index)
{
PhysPageEntry lp = d->phys_map;
PhysPageEntry *p;
@ -200,10 +199,28 @@ MemoryRegionSection *phys_page_find(AddressSpaceDispatch *d, hwaddr index)
bool memory_region_is_unassigned(MemoryRegion *mr)
{
return mr != &io_mem_ram && mr != &io_mem_rom
&& mr != &io_mem_notdirty && !mr->rom_device
return mr != &io_mem_rom && mr != &io_mem_notdirty && !mr->rom_device
&& mr != &io_mem_watch;
}
MemoryRegionSection *address_space_translate(AddressSpace *as, hwaddr addr,
hwaddr *xlat, hwaddr *plen,
bool is_write)
{
MemoryRegionSection *section;
Int128 diff;
section = phys_page_find(as->dispatch, addr >> TARGET_PAGE_BITS);
/* Compute offset within MemoryRegionSection */
addr -= section->offset_within_address_space;
/* Compute offset within MemoryRegion */
*xlat = addr + section->offset_within_region;
diff = int128_sub(section->mr->size, int128_make64(addr));
*plen = MIN(int128_get64(diff), *plen);
return section;
}
#endif
void cpu_exec_init_all(void)
@ -616,11 +633,11 @@ static int cpu_physical_memory_set_dirty_tracking(int enable)
}
hwaddr memory_region_section_get_iotlb(CPUArchState *env,
MemoryRegionSection *section,
target_ulong vaddr,
hwaddr paddr,
int prot,
target_ulong *address)
MemoryRegionSection *section,
target_ulong vaddr,
hwaddr paddr, hwaddr xlat,
int prot,
target_ulong *address)
{
hwaddr iotlb;
CPUWatchpoint *wp;
@ -628,7 +645,7 @@ hwaddr memory_region_section_get_iotlb(CPUArchState *env,
if (memory_region_is_ram(section->mr)) {
/* Normal RAM. */
iotlb = (memory_region_get_ram_addr(section->mr) & TARGET_PAGE_MASK)
+ memory_region_section_addr(section, paddr);
+ xlat;
if (!section->readonly) {
iotlb |= phys_section_notdirty;
} else {
@ -636,7 +653,7 @@ hwaddr memory_region_section_get_iotlb(CPUArchState *env,
}
} else {
iotlb = section - phys_sections;
iotlb += memory_region_section_addr(section, paddr);
iotlb += xlat;
}
/* Make accesses to pages with watchpoints go via the
@ -1384,69 +1401,14 @@ ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr)
return ram_addr;
}
static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
#ifdef DEBUG_UNASSIGNED
printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
#endif
#if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE)
cpu_unassigned_access(cpu_single_env, addr, 0, 0, 0, size);
#endif
return 0;
}
static void unassigned_mem_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
#ifdef DEBUG_UNASSIGNED
printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
#endif
#if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE)
cpu_unassigned_access(cpu_single_env, addr, 1, 0, 0, size);
#endif
}
static const MemoryRegionOps unassigned_mem_ops = {
.read = unassigned_mem_read,
.write = unassigned_mem_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static uint64_t error_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
abort();
}
static void error_mem_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
abort();
}
static const MemoryRegionOps error_mem_ops = {
.read = error_mem_read,
.write = error_mem_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static const MemoryRegionOps rom_mem_ops = {
.read = error_mem_read,
.write = unassigned_mem_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static void notdirty_mem_write(void *opaque, hwaddr ram_addr,
uint64_t val, unsigned size)
{
int dirty_flags;
dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr);
if (!(dirty_flags & CODE_DIRTY_FLAG)) {
#if !defined(CONFIG_USER_ONLY)
tb_invalidate_phys_page_fast(ram_addr, size);
dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr);
#endif
}
switch (size) {
case 1:
@ -1469,9 +1431,15 @@ static void notdirty_mem_write(void *opaque, hwaddr ram_addr,
tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
}
static bool notdirty_mem_accepts(void *opaque, hwaddr addr,
unsigned size, bool is_write)
{
return is_write;
}
static const MemoryRegionOps notdirty_mem_ops = {
.read = error_mem_read,
.write = notdirty_mem_write,
.valid.accepts = notdirty_mem_accepts,
.endianness = DEVICE_NATIVE_ENDIAN,
};
@ -1558,6 +1526,8 @@ static uint64_t subpage_read(void *opaque, hwaddr addr,
{
subpage_t *mmio = opaque;
unsigned int idx = SUBPAGE_IDX(addr);
uint64_t val;
MemoryRegionSection *section;
#if defined(DEBUG_SUBPAGE)
printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d\n", __func__,
@ -1568,7 +1538,8 @@ static uint64_t subpage_read(void *opaque, hwaddr addr,
addr += mmio->base;
addr -= section->offset_within_address_space;
addr += section->offset_within_region;
return io_mem_read(section->mr, addr, len);
io_mem_read(section->mr, addr, &val, len);
return val;
}
static void subpage_write(void *opaque, hwaddr addr,
@ -1590,9 +1561,29 @@ static void subpage_write(void *opaque, hwaddr addr,
io_mem_write(section->mr, addr, value, len);
}
static bool subpage_accepts(void *opaque, hwaddr addr,
unsigned size, bool is_write)
{
subpage_t *mmio = opaque;
unsigned int idx = SUBPAGE_IDX(addr);
MemoryRegionSection *section;
#if defined(DEBUG_SUBPAGE)
printf("%s: subpage %p %c len %d addr " TARGET_FMT_plx
" idx %d\n", __func__, mmio,
is_write ? 'w' : 'r', len, addr, idx);
#endif
section = &phys_sections[mmio->sub_section[idx]];
addr += mmio->base;
addr -= section->offset_within_address_space;
addr += section->offset_within_region;
return memory_region_access_valid(section->mr, addr, size, is_write);
}
static const MemoryRegionOps subpage_ops = {
.read = subpage_read,
.write = subpage_write,
.valid.accepts = subpage_accepts,
.endianness = DEVICE_NATIVE_ENDIAN,
};
@ -1691,8 +1682,7 @@ MemoryRegion *iotlb_to_region(hwaddr index)
static void io_mem_init(void)
{
memory_region_init_io(&io_mem_ram, &error_mem_ops, NULL, "ram", UINT64_MAX);
memory_region_init_io(&io_mem_rom, &rom_mem_ops, NULL, "rom", UINT64_MAX);
memory_region_init_io(&io_mem_rom, &unassigned_mem_ops, NULL, "rom", UINT64_MAX);
memory_region_init_io(&io_mem_unassigned, &unassigned_mem_ops, NULL,
"unassigned", UINT64_MAX);
memory_region_init_io(&io_mem_notdirty, &notdirty_mem_ops, NULL,
@ -1889,81 +1879,88 @@ static void invalidate_and_set_dirty(hwaddr addr,
xen_modified_memory(addr, length);
}
void address_space_rw(AddressSpace *as, hwaddr addr, uint8_t *buf,
static inline bool memory_access_is_direct(MemoryRegion *mr, bool is_write)
{
if (memory_region_is_ram(mr)) {
return !(is_write && mr->readonly);
}
if (memory_region_is_romd(mr)) {
return !is_write;
}
return false;
}
static inline int memory_access_size(int l, hwaddr addr)
{
if (l >= 4 && ((addr & 3) == 0)) {
return 4;
}
if (l >= 2 && ((addr & 1) == 0)) {
return 2;
}
return 1;
}
bool address_space_rw(AddressSpace *as, hwaddr addr, uint8_t *buf,
int len, bool is_write)
{
AddressSpaceDispatch *d = as->dispatch;
int l;
hwaddr l;
uint8_t *ptr;
uint32_t val;
hwaddr page;
uint64_t val;
hwaddr addr1;
MemoryRegionSection *section;
bool error = false;
while (len > 0) {
page = addr & TARGET_PAGE_MASK;
l = (page + TARGET_PAGE_SIZE) - addr;
if (l > len)
l = len;
section = phys_page_find(d, page >> TARGET_PAGE_BITS);
l = len;
section = address_space_translate(as, addr, &addr1, &l, is_write);
if (is_write) {
if (!memory_region_is_ram(section->mr)) {
hwaddr addr1;
addr1 = memory_region_section_addr(section, addr);
if (!memory_access_is_direct(section->mr, is_write)) {
l = memory_access_size(l, addr1);
/* XXX: could force cpu_single_env to NULL to avoid
potential bugs */
if (l >= 4 && ((addr1 & 3) == 0)) {
if (l == 4) {
/* 32 bit write access */
val = ldl_p(buf);
io_mem_write(section->mr, addr1, val, 4);
l = 4;
} else if (l >= 2 && ((addr1 & 1) == 0)) {
error |= io_mem_write(section->mr, addr1, val, 4);
} else if (l == 2) {
/* 16 bit write access */
val = lduw_p(buf);
io_mem_write(section->mr, addr1, val, 2);
l = 2;
error |= io_mem_write(section->mr, addr1, val, 2);
} else {
/* 8 bit write access */
val = ldub_p(buf);
io_mem_write(section->mr, addr1, val, 1);
l = 1;
error |= io_mem_write(section->mr, addr1, val, 1);
}
} else if (!section->readonly) {
ram_addr_t addr1;
addr1 = memory_region_get_ram_addr(section->mr)
+ memory_region_section_addr(section, addr);
} else {
addr1 += memory_region_get_ram_addr(section->mr);
/* RAM case */
ptr = qemu_get_ram_ptr(addr1);
memcpy(ptr, buf, l);
invalidate_and_set_dirty(addr1, l);
}
} else {
if (!(memory_region_is_ram(section->mr) ||
memory_region_is_romd(section->mr))) {
hwaddr addr1;
if (!memory_access_is_direct(section->mr, is_write)) {
/* I/O case */
addr1 = memory_region_section_addr(section, addr);
if (l >= 4 && ((addr1 & 3) == 0)) {
l = memory_access_size(l, addr1);
if (l == 4) {
/* 32 bit read access */
val = io_mem_read(section->mr, addr1, 4);
error |= io_mem_read(section->mr, addr1, &val, 4);
stl_p(buf, val);
l = 4;
} else if (l >= 2 && ((addr1 & 1) == 0)) {
} else if (l == 2) {
/* 16 bit read access */
val = io_mem_read(section->mr, addr1, 2);
error |= io_mem_read(section->mr, addr1, &val, 2);
stw_p(buf, val);
l = 2;
} else {
/* 8 bit read access */
val = io_mem_read(section->mr, addr1, 1);
error |= io_mem_read(section->mr, addr1, &val, 1);
stb_p(buf, val);
l = 1;
}
} else {
/* RAM case */
ptr = qemu_get_ram_ptr(section->mr->ram_addr
+ memory_region_section_addr(section,
addr));
ptr = qemu_get_ram_ptr(section->mr->ram_addr + addr1);
memcpy(buf, ptr, l);
}
}
@ -1971,57 +1968,47 @@ void address_space_rw(AddressSpace *as, hwaddr addr, uint8_t *buf,
buf += l;
addr += l;
}
return error;
}
void address_space_write(AddressSpace *as, hwaddr addr,
bool address_space_write(AddressSpace *as, hwaddr addr,
const uint8_t *buf, int len)
{
address_space_rw(as, addr, (uint8_t *)buf, len, true);
return address_space_rw(as, addr, (uint8_t *)buf, len, true);
}
/**
* address_space_read: read from an address space.
*
* @as: #AddressSpace to be accessed
* @addr: address within that address space
* @buf: buffer with the data transferred
*/
void address_space_read(AddressSpace *as, hwaddr addr, uint8_t *buf, int len)
bool address_space_read(AddressSpace *as, hwaddr addr, uint8_t *buf, int len)
{
address_space_rw(as, addr, buf, len, false);
return address_space_rw(as, addr, buf, len, false);
}
void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
int len, int is_write)
{
return address_space_rw(&address_space_memory, addr, buf, len, is_write);
address_space_rw(&address_space_memory, addr, buf, len, is_write);
}
/* used for ROM loading : can write in RAM and ROM */
void cpu_physical_memory_write_rom(hwaddr addr,
const uint8_t *buf, int len)
{
AddressSpaceDispatch *d = address_space_memory.dispatch;
int l;
hwaddr l;
uint8_t *ptr;
hwaddr page;
hwaddr addr1;
MemoryRegionSection *section;
while (len > 0) {
page = addr & TARGET_PAGE_MASK;
l = (page + TARGET_PAGE_SIZE) - addr;
if (l > len)
l = len;
section = phys_page_find(d, page >> TARGET_PAGE_BITS);
l = len;
section = address_space_translate(&address_space_memory,
addr, &addr1, &l, true);
if (!(memory_region_is_ram(section->mr) ||
memory_region_is_romd(section->mr))) {
/* do nothing */
} else {
unsigned long addr1;
addr1 = memory_region_get_ram_addr(section->mr)
+ memory_region_section_addr(section, addr);
addr1 += memory_region_get_ram_addr(section->mr);
/* ROM/RAM case */
ptr = qemu_get_ram_ptr(addr1);
memcpy(ptr, buf, l);
@ -2079,6 +2066,27 @@ static void cpu_notify_map_clients(void)
}
}
bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_write)
{
MemoryRegionSection *section;
hwaddr l, xlat;
while (len > 0) {
l = len;
section = address_space_translate(as, addr, &xlat, &l, is_write);
if (!memory_access_is_direct(section->mr, is_write)) {
l = memory_access_size(l, addr);
if (!memory_region_access_valid(section->mr, xlat, l, is_write)) {
return false;
}
}
len -= l;
addr += l;
}
return true;
}
/* Map a physical memory region into a host virtual address.
* May map a subset of the requested range, given by and returned in *plen.
* May return NULL if resources needed to perform the mapping are exhausted.
@ -2091,24 +2099,19 @@ void *address_space_map(AddressSpace *as,
hwaddr *plen,
bool is_write)
{
AddressSpaceDispatch *d = as->dispatch;
hwaddr len = *plen;
hwaddr todo = 0;
int l;
hwaddr page;
hwaddr l, xlat;
MemoryRegionSection *section;
ram_addr_t raddr = RAM_ADDR_MAX;
ram_addr_t rlen;
void *ret;
while (len > 0) {
page = addr & TARGET_PAGE_MASK;
l = (page + TARGET_PAGE_SIZE) - addr;
if (l > len)
l = len;
section = phys_page_find(d, page >> TARGET_PAGE_BITS);
l = len;
section = address_space_translate(as, addr, &xlat, &l, is_write);
if (!(memory_region_is_ram(section->mr) && !section->readonly)) {
if (!memory_access_is_direct(section->mr, is_write)) {
if (todo || bounce.buffer) {
break;
}
@ -2123,8 +2126,11 @@ void *address_space_map(AddressSpace *as,
return bounce.buffer;
}
if (!todo) {
raddr = memory_region_get_ram_addr(section->mr)
+ memory_region_section_addr(section, addr);
raddr = memory_region_get_ram_addr(section->mr) + xlat;
} else {
if (memory_region_get_ram_addr(section->mr) + xlat != raddr + todo) {
break;
}
}
len -= l;
@ -2188,16 +2194,16 @@ static inline uint32_t ldl_phys_internal(hwaddr addr,
enum device_endian endian)
{
uint8_t *ptr;
uint32_t val;
uint64_t val;
MemoryRegionSection *section;
hwaddr l = 4;
hwaddr addr1;
section = phys_page_find(address_space_memory.dispatch, addr >> TARGET_PAGE_BITS);
if (!(memory_region_is_ram(section->mr) ||
memory_region_is_romd(section->mr))) {
section = address_space_translate(&address_space_memory, addr, &addr1, &l,
false);
if (l < 4 || !memory_access_is_direct(section->mr, false)) {
/* I/O case */
addr = memory_region_section_addr(section, addr);
val = io_mem_read(section->mr, addr, 4);
io_mem_read(section->mr, addr1, &val, 4);
#if defined(TARGET_WORDS_BIGENDIAN)
if (endian == DEVICE_LITTLE_ENDIAN) {
val = bswap32(val);
@ -2211,7 +2217,7 @@ static inline uint32_t ldl_phys_internal(hwaddr addr,
/* RAM case */
ptr = qemu_get_ram_ptr((memory_region_get_ram_addr(section->mr)
& TARGET_PAGE_MASK)
+ memory_region_section_addr(section, addr));
+ addr1);
switch (endian) {
case DEVICE_LITTLE_ENDIAN:
val = ldl_le_p(ptr);
@ -2249,28 +2255,28 @@ static inline uint64_t ldq_phys_internal(hwaddr addr,
uint8_t *ptr;
uint64_t val;
MemoryRegionSection *section;
hwaddr l = 8;
hwaddr addr1;
section = phys_page_find(address_space_memory.dispatch, addr >> TARGET_PAGE_BITS);
if (!(memory_region_is_ram(section->mr) ||
memory_region_is_romd(section->mr))) {
section = address_space_translate(&address_space_memory, addr, &addr1, &l,
false);
if (l < 8 || !memory_access_is_direct(section->mr, false)) {
/* I/O case */
addr = memory_region_section_addr(section, addr);
/* XXX This is broken when device endian != cpu endian.
Fix and add "endian" variable check */
#ifdef TARGET_WORDS_BIGENDIAN
val = io_mem_read(section->mr, addr, 4) << 32;
val |= io_mem_read(section->mr, addr + 4, 4);
io_mem_read(section->mr, addr1, &val, 8);
#if defined(TARGET_WORDS_BIGENDIAN)
if (endian == DEVICE_LITTLE_ENDIAN) {
val = bswap64(val);
}
#else
val = io_mem_read(section->mr, addr, 4);
val |= io_mem_read(section->mr, addr + 4, 4) << 32;
if (endian == DEVICE_BIG_ENDIAN) {
val = bswap64(val);
}
#endif
} else {
/* RAM case */
ptr = qemu_get_ram_ptr((memory_region_get_ram_addr(section->mr)
& TARGET_PAGE_MASK)
+ memory_region_section_addr(section, addr));
+ addr1);
switch (endian) {
case DEVICE_LITTLE_ENDIAN:
val = ldq_le_p(ptr);
@ -2316,14 +2322,14 @@ static inline uint32_t lduw_phys_internal(hwaddr addr,
uint8_t *ptr;
uint64_t val;
MemoryRegionSection *section;
hwaddr l = 2;
hwaddr addr1;
section = phys_page_find(address_space_memory.dispatch, addr >> TARGET_PAGE_BITS);
if (!(memory_region_is_ram(section->mr) ||
memory_region_is_romd(section->mr))) {
section = address_space_translate(&address_space_memory, addr, &addr1, &l,
false);
if (l < 2 || !memory_access_is_direct(section->mr, false)) {
/* I/O case */
addr = memory_region_section_addr(section, addr);
val = io_mem_read(section->mr, addr, 2);
io_mem_read(section->mr, addr1, &val, 2);
#if defined(TARGET_WORDS_BIGENDIAN)
if (endian == DEVICE_LITTLE_ENDIAN) {
val = bswap16(val);
@ -2337,7 +2343,7 @@ static inline uint32_t lduw_phys_internal(hwaddr addr,
/* RAM case */
ptr = qemu_get_ram_ptr((memory_region_get_ram_addr(section->mr)
& TARGET_PAGE_MASK)
+ memory_region_section_addr(section, addr));
+ addr1);
switch (endian) {
case DEVICE_LITTLE_ENDIAN:
val = lduw_le_p(ptr);
@ -2375,19 +2381,15 @@ void stl_phys_notdirty(hwaddr addr, uint32_t val)
{
uint8_t *ptr;
MemoryRegionSection *section;
hwaddr l = 4;
hwaddr addr1;
section = phys_page_find(address_space_memory.dispatch, addr >> TARGET_PAGE_BITS);
if (!memory_region_is_ram(section->mr) || section->readonly) {
addr = memory_region_section_addr(section, addr);
if (memory_region_is_ram(section->mr)) {
section = &phys_sections[phys_section_rom];
}
io_mem_write(section->mr, addr, val, 4);
section = address_space_translate(&address_space_memory, addr, &addr1, &l,
true);
if (l < 4 || !memory_access_is_direct(section->mr, true)) {
io_mem_write(section->mr, addr1, val, 4);
} else {
unsigned long addr1 = (memory_region_get_ram_addr(section->mr)
& TARGET_PAGE_MASK)
+ memory_region_section_addr(section, addr);
addr1 += memory_region_get_ram_addr(section->mr) & TARGET_PAGE_MASK;
ptr = qemu_get_ram_ptr(addr1);
stl_p(ptr, val);
@ -2409,14 +2411,12 @@ static inline void stl_phys_internal(hwaddr addr, uint32_t val,
{
uint8_t *ptr;
MemoryRegionSection *section;
hwaddr l = 4;
hwaddr addr1;
section = phys_page_find(address_space_memory.dispatch, addr >> TARGET_PAGE_BITS);
if (!memory_region_is_ram(section->mr) || section->readonly) {
addr = memory_region_section_addr(section, addr);
if (memory_region_is_ram(section->mr)) {
section = &phys_sections[phys_section_rom];
}
section = address_space_translate(&address_space_memory, addr, &addr1, &l,
true);
if (l < 4 || !memory_access_is_direct(section->mr, true)) {
#if defined(TARGET_WORDS_BIGENDIAN)
if (endian == DEVICE_LITTLE_ENDIAN) {
val = bswap32(val);
@ -2426,12 +2426,10 @@ static inline void stl_phys_internal(hwaddr addr, uint32_t val,
val = bswap32(val);
}
#endif
io_mem_write(section->mr, addr, val, 4);
io_mem_write(section->mr, addr1, val, 4);
} else {
unsigned long addr1;
addr1 = (memory_region_get_ram_addr(section->mr) & TARGET_PAGE_MASK)
+ memory_region_section_addr(section, addr);
/* RAM case */
addr1 += memory_region_get_ram_addr(section->mr) & TARGET_PAGE_MASK;
ptr = qemu_get_ram_ptr(addr1);
switch (endian) {
case DEVICE_LITTLE_ENDIAN:
@ -2476,14 +2474,12 @@ static inline void stw_phys_internal(hwaddr addr, uint32_t val,
{
uint8_t *ptr;
MemoryRegionSection *section;
hwaddr l = 2;
hwaddr addr1;
section = phys_page_find(address_space_memory.dispatch, addr >> TARGET_PAGE_BITS);
if (!memory_region_is_ram(section->mr) || section->readonly) {
addr = memory_region_section_addr(section, addr);
if (memory_region_is_ram(section->mr)) {
section = &phys_sections[phys_section_rom];
}
section = address_space_translate(&address_space_memory, addr, &addr1, &l,
true);
if (l < 2 || !memory_access_is_direct(section->mr, true)) {
#if defined(TARGET_WORDS_BIGENDIAN)
if (endian == DEVICE_LITTLE_ENDIAN) {
val = bswap16(val);
@ -2493,12 +2489,10 @@ static inline void stw_phys_internal(hwaddr addr, uint32_t val,
val = bswap16(val);
}
#endif
io_mem_write(section->mr, addr, val, 2);
io_mem_write(section->mr, addr1, val, 2);
} else {
unsigned long addr1;
addr1 = (memory_region_get_ram_addr(section->mr) & TARGET_PAGE_MASK)
+ memory_region_section_addr(section, addr);
/* RAM case */
addr1 += memory_region_get_ram_addr(section->mr) & TARGET_PAGE_MASK;
ptr = qemu_get_ram_ptr(addr1);
switch (endian) {
case DEVICE_LITTLE_ENDIAN:
@ -2601,9 +2595,10 @@ bool virtio_is_big_endian(void)
bool cpu_physical_memory_is_io(hwaddr phys_addr)
{
MemoryRegionSection *section;
hwaddr l = 1;
section = phys_page_find(address_space_memory.dispatch,
phys_addr >> TARGET_PAGE_BITS);
section = address_space_translate(&address_space_memory,
phys_addr, &phys_addr, &l, false);
return !(memory_region_is_ram(section->mr) ||
memory_region_is_romd(section->mr));

2
include/exec/cpu-common.h
View File

@ -110,9 +110,7 @@ void stq_phys(hwaddr addr, uint64_t val);
void cpu_physical_memory_write_rom(hwaddr addr,
const uint8_t *buf, int len);
extern struct MemoryRegion io_mem_ram;
extern struct MemoryRegion io_mem_rom;
extern struct MemoryRegion io_mem_unassigned;
extern struct MemoryRegion io_mem_notdirty;
#endif

12
include/exec/cputlb.h
View File

@ -26,8 +26,6 @@ void tlb_unprotect_code_phys(CPUArchState *env, ram_addr_t ram_addr,
target_ulong vaddr);
void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, uintptr_t start,
uintptr_t length);
MemoryRegionSection *phys_page_find(struct AddressSpaceDispatch *d,
hwaddr index);
void cpu_tlb_reset_dirty_all(ram_addr_t start1, ram_addr_t length);
void tlb_set_dirty(CPUArchState *env, target_ulong vaddr);
extern int tlb_flush_count;
@ -35,11 +33,11 @@ extern int tlb_flush_count;
/* exec.c */
void tb_flush_jmp_cache(CPUArchState *env, target_ulong addr);
hwaddr memory_region_section_get_iotlb(CPUArchState *env,
MemoryRegionSection *section,
target_ulong vaddr,
hwaddr paddr,
int prot,
target_ulong *address);
MemoryRegionSection *section,
target_ulong vaddr,
hwaddr paddr, hwaddr xlat,
int prot,
target_ulong *address);
bool memory_region_is_unassigned(MemoryRegion *mr);
#endif

6
include/exec/exec-all.h
View File

@ -367,9 +367,9 @@ bool is_tcg_gen_code(uintptr_t pc_ptr);
#if !defined(CONFIG_USER_ONLY)
struct MemoryRegion *iotlb_to_region(hwaddr index);
uint64_t io_mem_read(struct MemoryRegion *mr, hwaddr addr,
unsigned size);
void io_mem_write(struct MemoryRegion *mr, hwaddr addr,
bool io_mem_read(struct MemoryRegion *mr, hwaddr addr,
uint64_t *pvalue, unsigned size);
bool io_mem_write(struct MemoryRegion *mr, hwaddr addr,
uint64_t value, unsigned size);
void tlb_fill(CPUArchState *env1, target_ulong addr, int is_write, int mmu_idx,

5
include/exec/memory-internal.h
View File

@ -43,6 +43,11 @@ struct AddressSpaceDispatch {
void address_space_init_dispatch(AddressSpace *as);
void address_space_destroy_dispatch(AddressSpace *as);
extern const MemoryRegionOps unassigned_mem_ops;
bool memory_region_access_valid(MemoryRegion *mr, hwaddr addr,
unsigned size, bool is_write);
ram_addr_t qemu_ram_alloc_from_ptr(ram_addr_t size, void *host,
MemoryRegion *mr);
ram_addr_t qemu_ram_alloc(ram_addr_t size, MemoryRegion *mr);

74
include/exec/memory.h
View File

@ -751,23 +751,6 @@ void memory_region_set_alias_offset(MemoryRegion *mr,
MemoryRegionSection memory_region_find(MemoryRegion *mr,
hwaddr addr, uint64_t size);
/**
* memory_region_section_addr: get offset within MemoryRegionSection
*
* Returns offset within MemoryRegionSection
*
* @section: the memory region section being queried
* @addr: address in address space
*/
static inline hwaddr
memory_region_section_addr(MemoryRegionSection *section,
hwaddr addr)
{
addr -= section->offset_within_address_space;
addr += section->offset_within_region;
return addr;
}
/**
* address_space_sync_dirty_bitmap: synchronize the dirty log for all memory
*
@ -842,32 +825,67 @@ void address_space_destroy(AddressSpace *as);
/**
* address_space_rw: read from or write to an address space.
*
* Return true if the operation hit any unassigned memory.
*
* @as: #AddressSpace to be accessed
* @addr: address within that address space
* @buf: buffer with the data transferred
* @is_write: indicates the transfer direction
*/
void address_space_rw(AddressSpace *as, hwaddr addr, uint8_t *buf,
bool address_space_rw(AddressSpace *as, hwaddr addr, uint8_t *buf,
int len, bool is_write);
/**
* address_space_write: write to address space.
*
* @as: #AddressSpace to be accessed
* @addr: address within that address space
* @buf: buffer with the data transferred
*/
void address_space_write(AddressSpace *as, hwaddr addr,
const uint8_t *buf, int len);
/**
* address_space_read: read from an address space.
* Return true if the operation hit any unassigned memory.
*
* @as: #AddressSpace to be accessed
* @addr: address within that address space
* @buf: buffer with the data transferred
*/
void address_space_read(AddressSpace *as, hwaddr addr, uint8_t *buf, int len);
bool address_space_write(AddressSpace *as, hwaddr addr,
const uint8_t *buf, int len);
/**
* address_space_read: read from an address space.
*
* Return true if the operation hit any unassigned memory.
*
* @as: #AddressSpace to be accessed
* @addr: address within that address space
* @buf: buffer with the data transferred
*/
bool address_space_read(AddressSpace *as, hwaddr addr, uint8_t *buf, int len);
/* address_space_translate: translate an address range into an address space
* into a MemoryRegionSection and an address range into that section
*
* @as: #AddressSpace to be accessed
* @addr: address within that address space
* @xlat: pointer to address within the returned memory region section's
* #MemoryRegion.
* @len: pointer to length
* @is_write: indicates the transfer direction
*/
MemoryRegionSection *address_space_translate(AddressSpace *as, hwaddr addr,
hwaddr *xlat, hwaddr *len,
bool is_write);
/* address_space_access_valid: check for validity of accessing an address
* space range
*
* Check whether memory is assigned to the given address space range.
*
* For now, addr and len should be aligned to a page size. This limitation
* will be lifted in the future.
*
* @as: #AddressSpace to be accessed
* @addr: address within that address space
* @len: length of the area to be checked
* @is_write: indicates the transfer direction
*/
bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_write);
/* address_space_map: map a physical memory region into a host virtual address
*

36
include/exec/softmmu_template.h
View File

@ -63,31 +63,18 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env,
target_ulong addr,
uintptr_t retaddr)
{
DATA_TYPE res;
uint64_t val;
MemoryRegion *mr = iotlb_to_region(physaddr);
physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
env->mem_io_pc = retaddr;
if (mr != &io_mem_ram && mr != &io_mem_rom
&& mr != &io_mem_unassigned
&& mr != &io_mem_notdirty
&& !can_do_io(env)) {
if (mr != &io_mem_rom && mr != &io_mem_notdirty && !can_do_io(env)) {
cpu_io_recompile(env, retaddr);
}
env->mem_io_vaddr = addr;
#if SHIFT <= 2
res = io_mem_read(mr, physaddr, 1 << SHIFT);
#else
#ifdef TARGET_WORDS_BIGENDIAN
res = io_mem_read(mr, physaddr, 4) << 32;
res |= io_mem_read(mr, physaddr + 4, 4);
#else
res = io_mem_read(mr, physaddr, 4);
res |= io_mem_read(mr, physaddr + 4, 4) << 32;
#endif
#endif /* SHIFT > 2 */
return res;
io_mem_read(mr, physaddr, &val, 1 << SHIFT);
return val;
}
/* handle all cases except unaligned access which span two pages */
@ -218,26 +205,13 @@ static inline void glue(io_write, SUFFIX)(CPUArchState *env,
MemoryRegion *mr = iotlb_to_region(physaddr);
physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
if (mr != &io_mem_ram && mr != &io_mem_rom
&& mr != &io_mem_unassigned
&& mr != &io_mem_notdirty
&& !can_do_io(env)) {
if (mr != &io_mem_rom && mr != &io_mem_notdirty && !can_do_io(env)) {
cpu_io_recompile(env, retaddr);
}
env->mem_io_vaddr = addr;
env->mem_io_pc = retaddr;
#if SHIFT <= 2
io_mem_write(mr, physaddr, val, 1 << SHIFT);
#else
#ifdef TARGET_WORDS_BIGENDIAN
io_mem_write(mr, physaddr, (val >> 32), 4);
io_mem_write(mr, physaddr + 4, (uint32_t)val, 4);
#else
io_mem_write(mr, physaddr, (uint32_t)val, 4);
io_mem_write(mr, physaddr + 4, val >> 32, 4);
#endif
#endif /* SHIFT > 2 */
}
void glue(glue(helper_st, SUFFIX), MMUSUFFIX)(CPUArchState *env,

3
include/sysemu/dma.h
View File

@ -113,7 +113,8 @@ static inline bool dma_memory_valid(DMAContext *dma,
DMADirection dir)
{
if (!dma_has_iommu(dma)) {
return true;
return address_space_access_valid(dma->as, addr, len,
dir == DMA_DIRECTION_FROM_DEVICE);
} else {
return iommu_dma_memory_valid(dma, addr, len, dir);
}

215
memory.c
View File

@ -22,6 +22,8 @@
#include "exec/memory-internal.h"
//#define DEBUG_UNASSIGNED
static unsigned memory_region_transaction_depth;
static bool memory_region_update_pending;
static bool global_dirty_log = false;
@ -300,6 +302,20 @@ static void flatview_simplify(FlatView *view)
}
}
static void memory_region_oldmmio_read_accessor(void *opaque,
hwaddr addr,
uint64_t *value,
unsigned size,
unsigned shift,
uint64_t mask)
{
MemoryRegion *mr = opaque;
uint64_t tmp;
tmp = mr->ops->old_mmio.read[ctz32(size)](mr->opaque, addr);
*value |= (tmp & mask) << shift;
}
static void memory_region_read_accessor(void *opaque,
hwaddr addr,
uint64_t *value,
@ -317,6 +333,20 @@ static void memory_region_read_accessor(void *opaque,
*value |= (tmp & mask) << shift;
}
static void memory_region_oldmmio_write_accessor(void *opaque,
hwaddr addr,
uint64_t *value,
unsigned size,
unsigned shift,
uint64_t mask)
{
MemoryRegion *mr = opaque;
uint64_t tmp;
tmp = (*value >> shift) & mask;
mr->ops->old_mmio.write[ctz32(size)](mr->opaque, addr, tmp);
}
static void memory_region_write_accessor(void *opaque,
hwaddr addr,
uint64_t *value,
@ -357,11 +387,17 @@ static void access_with_adjusted_size(hwaddr addr,
if (!access_size_max) {
access_size_max = 4;
}
/* FIXME: support unaligned access? */
access_size = MAX(MIN(size, access_size_max), access_size_min);
access_mask = -1ULL >> (64 - access_size * 8);
for (i = 0; i < size; i += access_size) {
/* FIXME: big-endian support */
#ifdef TARGET_WORDS_BIGENDIAN
access(opaque, addr + i, value, access_size,
(size - access_size - i) * 8, access_mask);
#else
access(opaque, addr + i, value, access_size, i * 8, access_mask);
#endif
}
}
@ -786,7 +822,8 @@ void memory_region_init(MemoryRegion *mr,
const char *name,
uint64_t size)
{
mr->ops = NULL;
mr->ops = &unassigned_mem_ops;
mr->opaque = NULL;
mr->parent = NULL;
mr->size = int128_make64(size);
if (size == UINT64_MAX) {
@ -814,29 +851,74 @@ void memory_region_init(MemoryRegion *mr,
mr->flush_coalesced_mmio = false;
}
static bool memory_region_access_valid(MemoryRegion *mr,
hwaddr addr,
unsigned size,
bool is_write)
static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
if (mr->ops->valid.accepts
&& !mr->ops->valid.accepts(mr->opaque, addr, size, is_write)) {
return false;
}
#ifdef DEBUG_UNASSIGNED
printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
#endif
#if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE)
cpu_unassigned_access(cpu_single_env, addr, 0, 0, 0, size);
#endif
return 0;
}
static void unassigned_mem_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
#ifdef DEBUG_UNASSIGNED
printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
#endif
#if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE)
cpu_unassigned_access(cpu_single_env, addr, 1, 0, 0, size);
#endif
}
static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
unsigned size, bool is_write)
{
return false;
}
const MemoryRegionOps unassigned_mem_ops = {
.valid.accepts = unassigned_mem_accepts,
.endianness = DEVICE_NATIVE_ENDIAN,
};
bool memory_region_access_valid(MemoryRegion *mr,
hwaddr addr,
unsigned size,
bool is_write)
{
int access_size_min, access_size_max;
int access_size, i;
if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
return false;
}
/* Treat zero as compatibility all valid */
if (!mr->ops->valid.max_access_size) {
if (!mr->ops->valid.accepts) {
return true;
}
if (size > mr->ops->valid.max_access_size
|| size < mr->ops->valid.min_access_size) {
return false;
access_size_min = mr->ops->valid.min_access_size;
if (!mr->ops->valid.min_access_size) {
access_size_min = 1;
}
access_size_max = mr->ops->valid.max_access_size;
if (!mr->ops->valid.max_access_size) {
access_size_max = 4;
}
access_size = MAX(MIN(size, access_size_max), access_size_min);
for (i = 0; i < size; i += access_size) {
if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
is_write)) {
return false;
}
}
return true;
}
@ -846,20 +928,16 @@ static uint64_t memory_region_dispatch_read1(MemoryRegion *mr,
{
uint64_t data = 0;
if (!memory_region_access_valid(mr, addr, size, false)) {
return -1U; /* FIXME: better signalling */
if (mr->ops->read) {
access_with_adjusted_size(addr, &data, size,
mr->ops->impl.min_access_size,
mr->ops->impl.max_access_size,
memory_region_read_accessor, mr);
} else {
access_with_adjusted_size(addr, &data, size, 1, 4,
memory_region_oldmmio_read_accessor, mr);
}
if (!mr->ops->read) {
return mr->ops->old_mmio.read[ctz32(size)](mr->opaque, addr);
}
/* FIXME: support unaligned access */
access_with_adjusted_size(addr, &data, size,
mr->ops->impl.min_access_size,
mr->ops->impl.max_access_size,
memory_region_read_accessor, mr);
return data;
}
@ -875,44 +953,52 @@ static void adjust_endianness(MemoryRegion *mr, uint64_t *data, unsigned size)
case 4:
*data = bswap32(*data);
break;
case 8:
*data = bswap64(*data);
break;
default:
abort();
}
}
}
static uint64_t memory_region_dispatch_read(MemoryRegion *mr,
hwaddr addr,
unsigned size)
static bool memory_region_dispatch_read(MemoryRegion *mr,
hwaddr addr,
uint64_t *pval,
unsigned size)
{
uint64_t ret;
if (!memory_region_access_valid(mr, addr, size, false)) {
*pval = unassigned_mem_read(mr, addr, size);
return true;
}
ret = memory_region_dispatch_read1(mr, addr, size);
adjust_endianness(mr, &ret, size);
return ret;
*pval = memory_region_dispatch_read1(mr, addr, size);
adjust_endianness(mr, pval, size);
return false;
}
static void memory_region_dispatch_write(MemoryRegion *mr,
static bool memory_region_dispatch_write(MemoryRegion *mr,
hwaddr addr,
uint64_t data,
unsigned size)
{
if (!memory_region_access_valid(mr, addr, size, true)) {
return; /* FIXME: better signalling */
unassigned_mem_write(mr, addr, data, size);
return true;
}
adjust_endianness(mr, &data, size);
if (!mr->ops->write) {
mr->ops->old_mmio.write[ctz32(size)](mr->opaque, addr, data);
return;
if (mr->ops->write) {
access_with_adjusted_size(addr, &data, size,
mr->ops->impl.min_access_size,
mr->ops->impl.max_access_size,
memory_region_write_accessor, mr);
} else {
access_with_adjusted_size(addr, &data, size, 1, 4,
memory_region_oldmmio_write_accessor, mr);
}
/* FIXME: support unaligned access */
access_with_adjusted_size(addr, &data, size,
mr->ops->impl.min_access_size,
mr->ops->impl.max_access_size,
memory_region_write_accessor, mr);
return false;
}
void memory_region_init_io(MemoryRegion *mr,
@ -977,40 +1063,11 @@ void memory_region_init_rom_device(MemoryRegion *mr,
mr->ram_addr = qemu_ram_alloc(size, mr);
}
static uint64_t invalid_read(void *opaque, hwaddr addr,
unsigned size)
{
MemoryRegion *mr = opaque;
if (!mr->warning_printed) {
fprintf(stderr, "Invalid read from memory region %s\n", mr->name);
mr->warning_printed = true;
}
return -1U;
}
static void invalid_write(void *opaque, hwaddr addr, uint64_t data,
unsigned size)
{
MemoryRegion *mr = opaque;
if (!mr->warning_printed) {
fprintf(stderr, "Invalid write to memory region %s\n", mr->name);
mr->warning_printed = true;
}
}
static const MemoryRegionOps reservation_ops = {
.read = invalid_read,
.write = invalid_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
void memory_region_init_reservation(MemoryRegion *mr,
const char *name,
uint64_t size)
{
memory_region_init_io(mr, &reservation_ops, mr, name, size);
memory_region_init_io(mr, &unassigned_mem_ops, mr, name, size);
}
void memory_region_destroy(MemoryRegion *mr)
@ -1594,15 +1651,15 @@ void address_space_destroy(AddressSpace *as)
g_free(as->ioeventfds);
}
uint64_t io_mem_read(MemoryRegion *mr, hwaddr addr, unsigned size)
bool io_mem_read(MemoryRegion *mr, hwaddr addr, uint64_t *pval, unsigned size)
{
return memory_region_dispatch_read(mr, addr, size);
return memory_region_dispatch_read(mr, addr, pval, size);
}
void io_mem_write(MemoryRegion *mr, hwaddr addr,
bool io_mem_write(MemoryRegion *mr, hwaddr addr,
uint64_t val, unsigned size)
{
memory_region_dispatch_write(mr, addr, val, size);
return memory_region_dispatch_write(mr, addr, val, size);
}
typedef struct MemoryRegionList MemoryRegionList;

6
translate-all.c
View File

@ -1354,15 +1354,15 @@ void tb_invalidate_phys_addr(hwaddr addr)
{
ram_addr_t ram_addr;
MemoryRegionSection *section;
hwaddr l = 1;
section = phys_page_find(address_space_memory.dispatch,
addr >> TARGET_PAGE_BITS);
section = address_space_translate(&address_space_memory, addr, &addr, &l, false);
if (!(memory_region_is_ram(section->mr)
|| memory_region_is_romd(section->mr))) {
return;
}
ram_addr = (memory_region_get_ram_addr(section->mr) & TARGET_PAGE_MASK)
+ memory_region_section_addr(section, addr);
+ addr;
tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0);
}
#endif /* TARGET_HAS_ICE && !defined(CONFIG_USER_ONLY) */