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target/arm: expose remaining CPUID registers as RAZ 

There are a whole bunch more registers in the CPUID space which are
currently not used but are exposed as RAZ. To avoid too much
duplication we expand ARMCPRegUserSpaceInfo to understand glob
patterns so we only need one entry to tweak whole ranges of registers.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20190205190224.2198-5-alex.bennee@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Alex Bennée 2019-02-15 09:56:39 +00:00 committed by Peter Maydell
parent 522641660c
commit d040242eff
2 changed files with 26 additions and 3 deletions
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3
target/arm/cpu.h
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@ -2474,6 +2474,9 @@ typedef struct ARMCPRegUserSpaceInfo {
/* Name of register */
const char *name;
/* Is the name actually a glob pattern */
bool is_glob;
/* Only some bits are exported to user space */
uint64_t exported_bits;

26
target/arm/helper.c
View File

@ -6109,19 +6109,27 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.fixed_bits = 0x0000000000000011 },
{ .name = "ID_AA64PFR1_EL1",
.exported_bits = 0x00000000000000f0 },
{ .name = "ID_AA64PFR*_EL1_RESERVED",
.is_glob = true },
{ .name = "ID_AA64ZFR0_EL1" },
{ .name = "ID_AA64MMFR0_EL1",
.fixed_bits = 0x00000000ff000000 },
{ .name = "ID_AA64MMFR1_EL1" },
{ .name = "ID_AA64MMFR*_EL1_RESERVED",
.is_glob = true },
{ .name = "ID_AA64DFR0_EL1",
.fixed_bits = 0x0000000000000006 },
{ .name = "ID_AA64DFR1_EL1" },
{ .name = "ID_AA64AFR0_EL1" },
{ .name = "ID_AA64AFR1_EL1" },
{ .name = "ID_AA64DFR*_EL1_RESERVED",
.is_glob = true },
{ .name = "ID_AA64AFR*",
.is_glob = true },
{ .name = "ID_AA64ISAR0_EL1",
.exported_bits = 0x00fffffff0fffff0 },
{ .name = "ID_AA64ISAR1_EL1",
.exported_bits = 0x000000f0ffffffff },
{ .name = "ID_AA64ISAR*_EL1_RESERVED",
.is_glob = true },
REGUSERINFO_SENTINEL
};
modify_arm_cp_regs(v8_idregs, v8_user_idregs);
@ -7020,8 +7028,17 @@ void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods)
ARMCPRegInfo *r;
for (m = mods; m->name; m++) {
GPatternSpec *pat = NULL;
if (m->is_glob) {
pat = g_pattern_spec_new(m->name);
}
for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
if (strcmp(r->name, m->name) == 0) {
if (pat && g_pattern_match_string(pat, r->name)) {
r->type = ARM_CP_CONST;
r->access = PL0U_R;
r->resetvalue = 0;
/* continue */
} else if (strcmp(r->name, m->name) == 0) {
r->type = ARM_CP_CONST;
r->access = PL0U_R;
r->resetvalue &= m->exported_bits;
@ -7029,6 +7046,9 @@ void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods)
break;
}
}
if (pat) {
g_pattern_spec_free(pat);
}
}
}