mirror of https://gitee.com/openkylin/qemu.git
libqos: add VIRTIO PCI 1.0 support
Implement the VIRTIO 1.0 virtio-pci interface. The main change here is that the register layout is no longer a fixed layout in BAR 0. Instead we have to iterate of PCI Capabilities to find descriptions of where various registers are located. The vring registers are also more fine-grained, allowing for more flexible vring layouts, but we don't take advantage of that. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Sergio Lopez <slp@redhat.com> Message-Id: <20191023100425.12168-17-stefanha@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com>
This commit is contained in:
Stefan Hajnoczi
Michael S. Tsirkin
parent
9598f9e402
commit
d08f68b8e8
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@ -723,6 +723,7 @@ qos-test-obj-y += tests/libqos/virtio-blk.o
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qos-test-obj-y += tests/libqos/virtio-mmio.o
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qos-test-obj-y += tests/libqos/virtio-net.o
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qos-test-obj-y += tests/libqos/virtio-pci.o
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qos-test-obj-y += tests/libqos/virtio-pci-modern.o
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qos-test-obj-y += tests/libqos/virtio-rng.o
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qos-test-obj-y += tests/libqos/virtio-scsi.o
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qos-test-obj-y += tests/libqos/virtio-serial.o
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@ -0,0 +1,443 @@
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/*
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* libqos VIRTIO 1.0 PCI driver
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*
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* Copyright (c) 2019 Red Hat, Inc
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "standard-headers/linux/pci_regs.h"
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#include "standard-headers/linux/virtio_pci.h"
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#include "standard-headers/linux/virtio_config.h"
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#include "virtio-pci-modern.h"
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static uint8_t config_readb(QVirtioDevice *d, uint64_t addr)
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{
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QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
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return qpci_io_readb(dev->pdev, dev->bar, dev->device_cfg_offset + addr);
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}
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static uint16_t config_readw(QVirtioDevice *d, uint64_t addr)
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{
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QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
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return qpci_io_readw(dev->pdev, dev->bar, dev->device_cfg_offset + addr);
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}
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static uint32_t config_readl(QVirtioDevice *d, uint64_t addr)
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{
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QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
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return qpci_io_readl(dev->pdev, dev->bar, dev->device_cfg_offset + addr);
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}
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static uint64_t config_readq(QVirtioDevice *d, uint64_t addr)
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{
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QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
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return qpci_io_readq(dev->pdev, dev->bar, dev->device_cfg_offset + addr);
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}
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static uint64_t get_features(QVirtioDevice *d)
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{
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QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
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uint64_t lo, hi;
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qpci_io_writel(dev->pdev, dev->bar, dev->common_cfg_offset +
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offsetof(struct virtio_pci_common_cfg,
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device_feature_select),
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0);
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lo = qpci_io_readl(dev->pdev, dev->bar, dev->common_cfg_offset +
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offsetof(struct virtio_pci_common_cfg, device_feature));
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qpci_io_writel(dev->pdev, dev->bar, dev->common_cfg_offset +
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offsetof(struct virtio_pci_common_cfg,
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device_feature_select),
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1);
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hi = qpci_io_readl(dev->pdev, dev->bar, dev->common_cfg_offset +
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offsetof(struct virtio_pci_common_cfg, device_feature));
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return (hi << 32) | lo;
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}
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static void set_features(QVirtioDevice *d, uint64_t features)
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{
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QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
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/* Drivers must enable VIRTIO 1.0 or else use the Legacy interface */
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g_assert_cmphex(features & (1ull << VIRTIO_F_VERSION_1), !=, 0);
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qpci_io_writel(dev->pdev, dev->bar, dev->common_cfg_offset +
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offsetof(struct virtio_pci_common_cfg,
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guest_feature_select),
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0);
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qpci_io_writel(dev->pdev, dev->bar, dev->common_cfg_offset +
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offsetof(struct virtio_pci_common_cfg,
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guest_feature),
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features);
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qpci_io_writel(dev->pdev, dev->bar, dev->common_cfg_offset +
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offsetof(struct virtio_pci_common_cfg,
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guest_feature_select),
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1);
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qpci_io_writel(dev->pdev, dev->bar, dev->common_cfg_offset +
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offsetof(struct virtio_pci_common_cfg,
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guest_feature),
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features >> 32);
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}
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static uint64_t get_guest_features(QVirtioDevice *d)
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{
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QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
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uint64_t lo, hi;
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qpci_io_writel(dev->pdev, dev->bar, dev->common_cfg_offset +
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offsetof(struct virtio_pci_common_cfg,
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guest_feature_select),
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0);
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lo = qpci_io_readl(dev->pdev, dev->bar, dev->common_cfg_offset +
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offsetof(struct virtio_pci_common_cfg, guest_feature));
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qpci_io_writel(dev->pdev, dev->bar, dev->common_cfg_offset +
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offsetof(struct virtio_pci_common_cfg,
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guest_feature_select),
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1);
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hi = qpci_io_readl(dev->pdev, dev->bar, dev->common_cfg_offset +
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offsetof(struct virtio_pci_common_cfg, guest_feature));
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return (hi << 32) | lo;
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}
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static uint8_t get_status(QVirtioDevice *d)
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{
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QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
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return qpci_io_readb(dev->pdev, dev->bar, dev->common_cfg_offset +
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offsetof(struct virtio_pci_common_cfg,
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device_status));
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}
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static void set_status(QVirtioDevice *d, uint8_t status)
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{
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QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
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return qpci_io_writeb(dev->pdev, dev->bar, dev->common_cfg_offset +
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offsetof(struct virtio_pci_common_cfg,
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device_status),
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status);
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}
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static bool get_msix_status(QVirtioPCIDevice *dev, uint32_t msix_entry,
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uint32_t msix_addr, uint32_t msix_data)
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{
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uint32_t data;
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g_assert_cmpint(msix_entry, !=, -1);
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if (qpci_msix_masked(dev->pdev, msix_entry)) {
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/* No ISR checking should be done if masked, but read anyway */
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return qpci_msix_pending(dev->pdev, msix_entry);
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}
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data = qtest_readl(dev->pdev->bus->qts, msix_addr);
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if (data == msix_data) {
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qtest_writel(dev->pdev->bus->qts, msix_addr, 0);
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return true;
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} else {
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return false;
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}
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}
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static bool get_queue_isr_status(QVirtioDevice *d, QVirtQueue *vq)
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{
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QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
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if (dev->pdev->msix_enabled) {
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QVirtQueuePCI *vqpci = container_of(vq, QVirtQueuePCI, vq);
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return get_msix_status(dev, vqpci->msix_entry, vqpci->msix_addr,
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vqpci->msix_data);
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}
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return qpci_io_readb(dev->pdev, dev->bar, dev->isr_cfg_offset) & 1;
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}
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static bool get_config_isr_status(QVirtioDevice *d)
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{
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QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
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if (dev->pdev->msix_enabled) {
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return get_msix_status(dev, dev->config_msix_entry,
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dev->config_msix_addr, dev->config_msix_data);
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}
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return qpci_io_readb(dev->pdev, dev->bar, dev->isr_cfg_offset) & 2;
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}
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static void wait_config_isr_status(QVirtioDevice *d, gint64 timeout_us)
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{
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QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
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gint64 start_time = g_get_monotonic_time();
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do {
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g_assert(g_get_monotonic_time() - start_time <= timeout_us);
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qtest_clock_step(dev->pdev->bus->qts, 100);
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} while (!get_config_isr_status(d));
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}
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static void queue_select(QVirtioDevice *d, uint16_t index)
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{
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QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
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qpci_io_writew(dev->pdev, dev->bar, dev->common_cfg_offset +
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offsetof(struct virtio_pci_common_cfg, queue_select),
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index);
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}
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static uint16_t get_queue_size(QVirtioDevice *d)
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{
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QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
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return qpci_io_readw(dev->pdev, dev->bar, dev->common_cfg_offset +
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offsetof(struct virtio_pci_common_cfg, queue_size));
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}
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static void set_queue_address(QVirtioDevice *d, QVirtQueue *vq)
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{
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QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
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qpci_io_writel(dev->pdev, dev->bar, dev->common_cfg_offset +
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offsetof(struct virtio_pci_common_cfg, queue_desc_lo),
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vq->desc);
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qpci_io_writel(dev->pdev, dev->bar, dev->common_cfg_offset +
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offsetof(struct virtio_pci_common_cfg, queue_desc_hi),
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vq->desc >> 32);
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qpci_io_writel(dev->pdev, dev->bar, dev->common_cfg_offset +
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offsetof(struct virtio_pci_common_cfg, queue_avail_lo),
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vq->avail);
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qpci_io_writel(dev->pdev, dev->bar, dev->common_cfg_offset +
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offsetof(struct virtio_pci_common_cfg, queue_avail_hi),
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vq->avail >> 32);
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qpci_io_writel(dev->pdev, dev->bar, dev->common_cfg_offset +
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offsetof(struct virtio_pci_common_cfg, queue_used_lo),
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vq->used);
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qpci_io_writel(dev->pdev, dev->bar, dev->common_cfg_offset +
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offsetof(struct virtio_pci_common_cfg, queue_used_hi),
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vq->used >> 32);
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}
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static QVirtQueue *virtqueue_setup(QVirtioDevice *d, QGuestAllocator *alloc,
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uint16_t index)
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{
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QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
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QVirtQueue *vq;
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QVirtQueuePCI *vqpci;
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uint16_t notify_off;
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vq = qvirtio_pci_virtqueue_setup_common(d, alloc, index);
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vqpci = container_of(vq, QVirtQueuePCI, vq);
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notify_off = qpci_io_readw(dev->pdev, dev->bar, dev->common_cfg_offset +
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offsetof(struct virtio_pci_common_cfg,
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queue_notify_off));
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vqpci->notify_offset = dev->notify_cfg_offset +
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notify_off * dev->notify_off_multiplier;
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qpci_io_writew(dev->pdev, dev->bar, dev->common_cfg_offset +
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offsetof(struct virtio_pci_common_cfg, queue_enable), 1);
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return vq;
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}
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static void virtqueue_kick(QVirtioDevice *d, QVirtQueue *vq)
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{
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QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
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QVirtQueuePCI *vqpci = container_of(vq, QVirtQueuePCI, vq);
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qpci_io_writew(dev->pdev, dev->bar, vqpci->notify_offset, vq->index);
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}
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static const QVirtioBus qvirtio_pci_virtio_1 = {
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.config_readb = config_readb,
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.config_readw = config_readw,
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.config_readl = config_readl,
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.config_readq = config_readq,
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.get_features = get_features,
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.set_features = set_features,
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.get_guest_features = get_guest_features,
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.get_status = get_status,
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.set_status = set_status,
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.get_queue_isr_status = get_queue_isr_status,
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.wait_config_isr_status = wait_config_isr_status,
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.queue_select = queue_select,
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.get_queue_size = get_queue_size,
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.set_queue_address = set_queue_address,
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.virtqueue_setup = virtqueue_setup,
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.virtqueue_cleanup = qvirtio_pci_virtqueue_cleanup_common,
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.virtqueue_kick = virtqueue_kick,
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};
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static void set_config_vector(QVirtioPCIDevice *d, uint16_t entry)
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{
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uint16_t vector;
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qpci_io_writew(d->pdev, d->bar, d->common_cfg_offset +
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offsetof(struct virtio_pci_common_cfg, msix_config), entry);
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vector = qpci_io_readw(d->pdev, d->bar, d->common_cfg_offset +
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offsetof(struct virtio_pci_common_cfg,
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msix_config));
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g_assert_cmphex(vector, !=, VIRTIO_MSI_NO_VECTOR);
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}
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static void set_queue_vector(QVirtioPCIDevice *d, uint16_t vq_idx,
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uint16_t entry)
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{
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uint16_t vector;
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queue_select(&d->vdev, vq_idx);
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qpci_io_writew(d->pdev, d->bar, d->common_cfg_offset +
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offsetof(struct virtio_pci_common_cfg, queue_msix_vector),
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entry);
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vector = qpci_io_readw(d->pdev, d->bar, d->common_cfg_offset +
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offsetof(struct virtio_pci_common_cfg,
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queue_msix_vector));
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g_assert_cmphex(vector, !=, VIRTIO_MSI_NO_VECTOR);
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}
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static const QVirtioPCIMSIXOps qvirtio_pci_msix_ops_virtio_1 = {
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.set_config_vector = set_config_vector,
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.set_queue_vector = set_queue_vector,
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};
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static bool probe_device_type(QVirtioPCIDevice *dev)
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{
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uint16_t vendor_id;
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uint16_t device_id;
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/* "Drivers MUST match devices with the PCI Vendor ID 0x1AF4" */
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vendor_id = qpci_config_readw(dev->pdev, PCI_VENDOR_ID);
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if (vendor_id != 0x1af4) {
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return false;
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}
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/*
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* "Any PCI device with ... PCI Device ID 0x1000 through 0x107F inclusive
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* is a virtio device"
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*/
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device_id = qpci_config_readw(dev->pdev, PCI_DEVICE_ID);
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if (device_id < 0x1000 || device_id > 0x107f) {
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return false;
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}
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/*
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* "Devices MAY utilize a Transitional PCI Device ID range, 0x1000 to
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* 0x103F depending on the device type"
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*/
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if (device_id < 0x1040) {
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/*
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* "Transitional devices MUST have the PCI Subsystem Device ID matching
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* the Virtio Device ID"
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*/
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dev->vdev.device_type = qpci_config_readw(dev->pdev, PCI_SUBSYSTEM_ID);
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} else {
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/*
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* "The PCI Device ID is calculated by adding 0x1040 to the Virtio
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* Device ID"
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*/
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dev->vdev.device_type = device_id - 0x1040;
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}
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return true;
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}
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/* Find the first VIRTIO 1.0 PCI structure for a given type */
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static bool find_structure(QVirtioPCIDevice *dev, uint8_t cfg_type,
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uint8_t *bar, uint32_t *offset, uint32_t *length,
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uint8_t *cfg_addr)
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{
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uint8_t addr = 0;
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while ((addr = qpci_find_capability(dev->pdev, PCI_CAP_ID_VNDR,
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addr)) != 0) {
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uint8_t type;
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type = qpci_config_readb(dev->pdev,
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addr + offsetof(struct virtio_pci_cap, cfg_type));
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if (type != cfg_type) {
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continue;
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}
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*bar = qpci_config_readb(dev->pdev,
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addr + offsetof(struct virtio_pci_cap, bar));
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*offset = qpci_config_readl(dev->pdev,
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addr + offsetof(struct virtio_pci_cap, offset));
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*length = qpci_config_readl(dev->pdev,
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addr + offsetof(struct virtio_pci_cap, length));
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if (cfg_addr) {
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*cfg_addr = addr;
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}
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return true;
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}
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return false;
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}
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static bool probe_device_layout(QVirtioPCIDevice *dev)
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{
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uint8_t bar;
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uint8_t cfg_addr;
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uint32_t length;
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/*
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* Due to the qpci_iomap() API we only support devices that put all
|
||||
* structures in the same PCI BAR. Luckily this is true with QEMU.
|
||||
*/
|
||||
|
||||
if (!find_structure(dev, VIRTIO_PCI_CAP_COMMON_CFG, &bar,
|
||||
&dev->common_cfg_offset, &length, NULL)) {
|
||||
return false;
|
||||
}
|
||||
dev->bar_idx = bar;
|
||||
|
||||
if (!find_structure(dev, VIRTIO_PCI_CAP_NOTIFY_CFG, &bar,
|
||||
&dev->notify_cfg_offset, &length, &cfg_addr)) {
|
||||
return false;
|
||||
}
|
||||
g_assert_cmphex(bar, ==, dev->bar_idx);
|
||||
|
||||
dev->notify_off_multiplier = qpci_config_readl(dev->pdev,
|
||||
cfg_addr + offsetof(struct virtio_pci_notify_cap,
|
||||
notify_off_multiplier));
|
||||
|
||||
if (!find_structure(dev, VIRTIO_PCI_CAP_ISR_CFG, &bar,
|
||||
&dev->isr_cfg_offset, &length, NULL)) {
|
||||
return false;
|
||||
}
|
||||
g_assert_cmphex(bar, ==, dev->bar_idx);
|
||||
|
||||
if (!find_structure(dev, VIRTIO_PCI_CAP_DEVICE_CFG, &bar,
|
||||
&dev->device_cfg_offset, &length, NULL)) {
|
||||
return false;
|
||||
}
|
||||
g_assert_cmphex(bar, ==, dev->bar_idx);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/* Probe a VIRTIO 1.0 device */
|
||||
bool qvirtio_pci_init_virtio_1(QVirtioPCIDevice *dev)
|
||||
{
|
||||
if (!probe_device_type(dev)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
if (!probe_device_layout(dev)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
dev->vdev.bus = &qvirtio_pci_virtio_1;
|
||||
dev->msix_ops = &qvirtio_pci_msix_ops_virtio_1;
|
||||
dev->vdev.big_endian = false;
|
||||
return true;
|
||||
}
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
/*
|
||||
* libqos virtio PCI VIRTIO 1.0 definitions
|
||||
*
|
||||
* Copyright (c) 2019 Red Hat, Inc
|
||||
*
|
||||
* This work is licensed under the terms of the GNU GPL, version 2 or later.
|
||||
* See the COPYING file in the top-level directory.
|
||||
*/
|
||||
|
||||
#ifndef LIBQOS_VIRTIO_PCI_MODERN_H
|
||||
#define LIBQOS_VIRTIO_PCI_MODERN_H
|
||||
|
||||
#include "virtio-pci.h"
|
||||
|
||||
bool qvirtio_pci_init_virtio_1(QVirtioPCIDevice *dev);
|
||||
|
||||
#endif /* LIBQOS_VIRTIO_PCI_MODERN_H */
|
||||
|
|
@ -22,6 +22,8 @@
|
|||
#include "hw/pci/pci.h"
|
||||
#include "hw/pci/pci_regs.h"
|
||||
|
||||
#include "virtio-pci-modern.h"
|
||||
|
||||
/* virtio-pci is a superclass of all virtio-xxx-pci devices;
|
||||
* the relation between virtio-pci and virtio-xxx-pci is implicit,
|
||||
* and therefore virtio-pci does not produce virtio and is not
|
||||
|
|
@ -401,7 +403,9 @@ static void qvirtio_pci_init_from_pcidev(QVirtioPCIDevice *dev, QPCIDevice *pci_
|
|||
dev->pdev = pci_dev;
|
||||
dev->config_msix_entry = -1;
|
||||
|
||||
qvirtio_pci_init_legacy(dev);
|
||||
if (!qvirtio_pci_init_virtio_1(dev)) {
|
||||
qvirtio_pci_init_legacy(dev);
|
||||
}
|
||||
|
||||
/* each virtio-xxx-pci device should override at least this function */
|
||||
dev->obj.get_driver = NULL;
|
||||
|
|
|
|||
|
|
@ -27,6 +27,13 @@ typedef struct QVirtioPCIDevice {
|
|||
uint32_t config_msix_data;
|
||||
|
||||
int bar_idx;
|
||||
|
||||
/* VIRTIO 1.0 */
|
||||
uint32_t common_cfg_offset;
|
||||
uint32_t notify_cfg_offset;
|
||||
uint32_t notify_off_multiplier;
|
||||
uint32_t isr_cfg_offset;
|
||||
uint32_t device_cfg_offset;
|
||||
} QVirtioPCIDevice;
|
||||
|
||||
struct QVirtioPCIMSIXOps {
|
||||
|
|
@ -43,6 +50,9 @@ typedef struct QVirtQueuePCI {
|
|||
uint16_t msix_entry;
|
||||
uint64_t msix_addr;
|
||||
uint32_t msix_data;
|
||||
|
||||
/* VIRTIO 1.0 */
|
||||
uint64_t notify_offset;
|
||||
} QVirtQueuePCI;
|
||||
|
||||
void virtio_pci_init(QVirtioPCIDevice *dev, QPCIBus *bus, QPCIAddress * addr);
|
||||
|
|
|
|||
Loading…
Reference in New Issue