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target/arm: Fix offsets for TTBCR 

The functions vmsa_ttbcr_write and vmsa_ttbcr_raw_write expect
the offset to be for the complete TCR structure, not the offset
to the low 32-bits of a uint64_t.  Using offsetoflow32 in this
case breaks big-endian hosts.

For TTBCR2, we do want the high 32-bits of a uint64_t.
Use cp15.tcr_el[*].raw_tcr as the offsetofhigh32 argument to
clarify this.

Buglink: https://gitlab.com/qemu-project/qemu/-/issues/187
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210709230621.938821-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2021-07-09 16:06:21 -07:00 committed by Peter Maydell
parent a97fca4ceb
commit d102058e79
1 changed files with 7 additions and 4 deletions
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11
target/arm/helper.c
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@ -4106,8 +4106,9 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
.access = PL1_RW, .accessfn = access_tvm_trvm,
.type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write,
.raw_writefn = vmsa_ttbcr_raw_write,
.bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]),
offsetoflow32(CPUARMState, cp15.tcr_el[1])} },
/* No offsetoflow32 -- pass the entire TCR to writefn/raw_writefn. */
.bank_fieldoffsets = { offsetof(CPUARMState, cp15.tcr_el[3]),
offsetof(CPUARMState, cp15.tcr_el[1])} },
REGINFO_SENTINEL
};
@ -4118,8 +4119,10 @@ static const ARMCPRegInfo ttbcr2_reginfo = {
.name = "TTBCR2", .cp = 15, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 3,
.access = PL1_RW, .accessfn = access_tvm_trvm,
.type = ARM_CP_ALIAS,
.bank_fieldoffsets = { offsetofhigh32(CPUARMState, cp15.tcr_el[3]),
offsetofhigh32(CPUARMState, cp15.tcr_el[1]) },
.bank_fieldoffsets = {
offsetofhigh32(CPUARMState, cp15.tcr_el[3].raw_tcr),
offsetofhigh32(CPUARMState, cp15.tcr_el[1].raw_tcr),
},
};
static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,