mirror of https://gitee.com/openkylin/qemu.git
initial support for up to 255 CPUs
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1707 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
parent
01dbbdf1e5
commit
d3e9db933f
236
hw/apic.c
236
hw/apic.c
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@ -60,6 +60,9 @@
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#define APIC_SV_ENABLE (1 << 8)
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#define MAX_APICS 255
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#define MAX_APIC_WORDS 8
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typedef struct APICState {
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CPUState *cpu_env;
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uint32_t apicbase;
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@ -81,8 +84,6 @@ typedef struct APICState {
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uint32_t initial_count;
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int64_t initial_count_load_time, next_time;
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QEMUTimer *timer;
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struct APICState *next_apic;
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} APICState;
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struct IOAPICState {
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@ -94,14 +95,95 @@ struct IOAPICState {
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};
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static int apic_io_memory;
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static APICState *first_local_apic = NULL;
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static APICState *local_apics[MAX_APICS + 1];
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static int last_apic_id = 0;
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static void apic_init_ipi(APICState *s);
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static void apic_set_irq(APICState *s, int vector_num, int trigger_mode);
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static void apic_update_irq(APICState *s);
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static void apic_bus_deliver(uint32_t deliver_bitmask, uint8_t delivery_mode,
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/* Find first bit starting from msb. Return 0 if value = 0 */
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static int fls_bit(uint32_t value)
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{
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unsigned int ret = 0;
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#if defined(HOST_I386)
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__asm__ __volatile__ ("bsr %1, %0\n" : "+r" (ret) : "rm" (value));
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return ret;
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#else
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if (value > 0xffff)
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value >>= 16, ret = 16;
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if (value > 0xff)
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value >>= 8, ret += 8;
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if (value > 0xf)
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value >>= 4, ret += 4;
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if (value > 0x3)
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value >>= 2, ret += 2;
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return ret + (value >> 1);
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#endif
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}
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/* Find first bit starting from lsb. Return 0 if value = 0 */
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static int ffs_bit(uint32_t value)
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{
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unsigned int ret = 0;
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#if defined(HOST_I386)
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__asm__ __volatile__ ("bsf %1, %0\n" : "+r" (ret) : "rm" (value));
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return ret;
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#else
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if (!value)
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return 0;
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if (!(value & 0xffff))
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value >>= 16, ret = 16;
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if (!(value & 0xff))
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value >>= 8, ret += 8;
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if (!(value & 0xf))
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value >>= 4, ret += 4;
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if (!(value & 0x3))
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value >>= 2, ret += 2;
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if (!(value & 0x1))
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ret++;
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return ret;
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#endif
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}
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static inline void set_bit(uint32_t *tab, int index)
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{
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int i, mask;
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i = index >> 5;
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mask = 1 << (index & 0x1f);
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tab[i] |= mask;
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}
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static inline void reset_bit(uint32_t *tab, int index)
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{
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int i, mask;
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i = index >> 5;
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mask = 1 << (index & 0x1f);
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tab[i] &= ~mask;
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}
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#define foreach_apic(apic, deliver_bitmask, code) \
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{\
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int __i, __j, __mask;\
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for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
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__mask = deliver_bitmask[__i];\
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if (__mask) {\
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for(__j = 0; __j < 32; __j++) {\
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if (__mask & (1 << __j)) {\
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apic = local_apics[__i * 32 + __j];\
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if (apic) {\
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code;\
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}\
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}\
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}\
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}\
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}\
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}
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static void apic_bus_deliver(const uint32_t *deliver_bitmask,
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uint8_t delivery_mode,
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uint8_t vector_num, uint8_t polarity,
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uint8_t trigger_mode)
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{
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@ -110,13 +192,23 @@ static void apic_bus_deliver(uint32_t deliver_bitmask, uint8_t delivery_mode,
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switch (delivery_mode) {
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case APIC_DM_LOWPRI:
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/* XXX: search for focus processor, arbitration */
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if (deliver_bitmask) {
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uint32_t m = 1;
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while ((deliver_bitmask & m) == 0)
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m <<= 1;
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deliver_bitmask = m;
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}
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{
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int i, d;
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d = -1;
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for(i = 0; i < MAX_APIC_WORDS; i++) {
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if (deliver_bitmask[i]) {
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d = i * 32 + ffs_bit(deliver_bitmask[i]);
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break;
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}
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}
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if (d >= 0) {
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apic_iter = local_apics[d];
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if (apic_iter) {
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apic_set_irq(apic_iter, vector_num, trigger_mode);
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}
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}
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}
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return;
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case APIC_DM_FIXED:
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break;
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@ -127,11 +219,8 @@ static void apic_bus_deliver(uint32_t deliver_bitmask, uint8_t delivery_mode,
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case APIC_DM_INIT:
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/* normal INIT IPI sent to processors */
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for (apic_iter = first_local_apic; apic_iter != NULL;
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apic_iter = apic_iter->next_apic) {
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if (deliver_bitmask & (1 << apic_iter->id))
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apic_init_ipi(apic_iter);
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}
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foreach_apic(apic_iter, deliver_bitmask,
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apic_init_ipi(apic_iter) );
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return;
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case APIC_DM_EXTINT:
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@ -142,11 +231,8 @@ static void apic_bus_deliver(uint32_t deliver_bitmask, uint8_t delivery_mode,
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return;
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}
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for (apic_iter = first_local_apic; apic_iter != NULL;
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apic_iter = apic_iter->next_apic) {
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if (deliver_bitmask & (1 << apic_iter->id))
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apic_set_irq(apic_iter, vector_num, trigger_mode);
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}
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foreach_apic(apic_iter, deliver_bitmask,
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apic_set_irq(apic_iter, vector_num, trigger_mode) );
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}
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void cpu_set_apic_base(CPUState *env, uint64_t val)
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@ -187,42 +273,6 @@ uint8_t cpu_get_apic_tpr(CPUX86State *env)
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return s->tpr >> 4;
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}
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static int fls_bit(int value)
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{
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unsigned int ret = 0;
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#ifdef HOST_I386
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__asm__ __volatile__ ("bsr %1, %0\n" : "+r" (ret) : "rm" (value));
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return ret;
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#else
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if (value > 0xffff)
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value >>= 16, ret = 16;
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if (value > 0xff)
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value >>= 8, ret += 8;
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if (value > 0xf)
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value >>= 4, ret += 4;
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if (value > 0x3)
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value >>= 2, ret += 2;
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return ret + (value >> 1);
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#endif
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}
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static inline void set_bit(uint32_t *tab, int index)
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{
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int i, mask;
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i = index >> 5;
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mask = 1 << (index & 0x1f);
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tab[i] |= mask;
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}
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static inline void reset_bit(uint32_t *tab, int index)
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{
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int i, mask;
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i = index >> 5;
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mask = 1 << (index & 0x1f);
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tab[i] &= ~mask;
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}
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/* return -1 if no bit is set */
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static int get_highest_priority_int(uint32_t *tab)
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{
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@ -294,26 +344,37 @@ static void apic_eoi(APICState *s)
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apic_update_irq(s);
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}
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static uint32_t apic_get_delivery_bitmask(uint8_t dest, uint8_t dest_mode)
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static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
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uint8_t dest, uint8_t dest_mode)
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{
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uint32_t mask = 0;
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APICState *apic_iter;
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int i;
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if (dest_mode == 0) {
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if (dest == 0xff)
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mask = 0xff;
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else
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mask = 1 << dest;
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if (dest == 0xff) {
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memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t));
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} else {
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memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
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set_bit(deliver_bitmask, dest);
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}
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} else {
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/* XXX: cluster mode */
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for (apic_iter = first_local_apic; apic_iter != NULL;
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apic_iter = apic_iter->next_apic) {
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memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
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for(i = 0; i < MAX_APICS; i++) {
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apic_iter = local_apics[i];
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if (apic_iter) {
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if (apic_iter->dest_mode == 0xf) {
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if (dest & apic_iter->log_dest)
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mask |= (1 << apic_iter->id);
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set_bit(deliver_bitmask, i);
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} else if (apic_iter->dest_mode == 0x0) {
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if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
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(dest & apic_iter->log_dest & 0x0f)) {
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set_bit(deliver_bitmask, i);
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}
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}
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}
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}
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}
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return mask;
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}
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@ -356,22 +417,24 @@ static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode,
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uint8_t delivery_mode, uint8_t vector_num,
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uint8_t polarity, uint8_t trigger_mode)
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{
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uint32_t deliver_bitmask = 0;
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uint32_t deliver_bitmask[MAX_APIC_WORDS];
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int dest_shorthand = (s->icr[0] >> 18) & 3;
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APICState *apic_iter;
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switch (dest_shorthand) {
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case 0:
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deliver_bitmask = apic_get_delivery_bitmask(dest, dest_mode);
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apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
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break;
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case 1:
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deliver_bitmask = (1 << s->id);
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memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
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set_bit(deliver_bitmask, s->id);
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break;
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case 2:
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deliver_bitmask = 0xffffffff;
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memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
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break;
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case 3:
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deliver_bitmask = 0xffffffff & ~(1 << s->id);
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memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
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reset_bit(deliver_bitmask, s->id);
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break;
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}
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@ -381,24 +444,16 @@ static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode,
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int trig_mode = (s->icr[0] >> 15) & 1;
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int level = (s->icr[0] >> 14) & 1;
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if (level == 0 && trig_mode == 1) {
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for (apic_iter = first_local_apic; apic_iter != NULL;
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apic_iter = apic_iter->next_apic) {
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if (deliver_bitmask & (1 << apic_iter->id)) {
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apic_iter->arb_id = apic_iter->id;
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}
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}
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foreach_apic(apic_iter, deliver_bitmask,
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apic_iter->arb_id = apic_iter->id );
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return;
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}
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}
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break;
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case APIC_DM_SIPI:
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for (apic_iter = first_local_apic; apic_iter != NULL;
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apic_iter = apic_iter->next_apic) {
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if (deliver_bitmask & (1 << apic_iter->id)) {
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apic_startup(apic_iter, vector_num);
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}
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}
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foreach_apic(apic_iter, deliver_bitmask,
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apic_startup(apic_iter, vector_num) );
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return;
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}
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@ -749,6 +804,8 @@ int apic_init(CPUState *env)
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{
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APICState *s;
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if (last_apic_id >= MAX_APICS)
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return -1;
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s = qemu_mallocz(sizeof(APICState));
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if (!s)
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return -1;
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@ -773,9 +830,7 @@ int apic_init(CPUState *env)
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register_savevm("apic", 0, 1, apic_save, apic_load, s);
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qemu_register_reset(apic_reset, s);
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s->next_apic = first_local_apic;
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first_local_apic = s;
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local_apics[s->id] = s;
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return 0;
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}
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@ -790,6 +845,7 @@ static void ioapic_service(IOAPICState *s)
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uint8_t dest;
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uint8_t dest_mode;
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uint8_t polarity;
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uint32_t deliver_bitmask[MAX_APIC_WORDS];
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for (i = 0; i < IOAPIC_NUM_PINS; i++) {
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mask = 1 << i;
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@ -807,8 +863,10 @@ static void ioapic_service(IOAPICState *s)
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vector = pic_read_irq(isa_pic);
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else
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vector = entry & 0xff;
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apic_bus_deliver(apic_get_delivery_bitmask(dest, dest_mode),
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delivery_mode, vector, polarity, trig_mode);
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apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
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apic_bus_deliver(deliver_bitmask, delivery_mode,
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vector, polarity, trig_mode);
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}
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}
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}
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6
vl.c
6
vl.c
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@ -153,10 +153,12 @@ USBPort *vm_usb_ports[MAX_VM_USB_PORTS];
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USBDevice *vm_usb_hub;
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static VLANState *first_vlan;
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int smp_cpus = 1;
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#ifdef TARGET_SPARC
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#if defined(TARGET_SPARC)
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#define MAX_CPUS 16
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#elif defined(TARGET_I386)
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#define MAX_CPUS 255
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#else
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#define MAX_CPUS 8
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#define MAX_CPUS 1
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#endif
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/***********************************************************/
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