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x86: Run qemu_inject_x86_mce on target VCPU 

We will use the current TCG-only MCE injection path for KVM as well, and
then this read-modify-write of the target VCPU state has to be performed
synchronously in the corresponding thread.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
This commit is contained in:
Jan Kiszka 2011-03-02 08:56:15 +01:00 committed by Marcelo Tosatti
parent ab443475c9
commit d5bfda334a
1 changed files with 58 additions and 29 deletions
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87
target-i386/helper.c
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@ -1067,29 +1067,42 @@ static void breakpoint_handler(CPUState *env)
prev_debug_excp_handler(env); prev_debug_excp_handler(env);
} }
static void typedef struct MCEInjectionParams {
qemu_inject_x86_mce(Monitor *mon, CPUState *cenv, int bank, uint64_t status, Monitor *mon;
uint64_t mcg_status, uint64_t addr, uint64_t misc, CPUState *env;
int flags) int bank;
uint64_t status;
uint64_t mcg_status;
uint64_t addr;
uint64_t misc;
int flags;
} MCEInjectionParams;
static void do_inject_x86_mce(void *data)
{ {
uint64_t mcg_cap = cenv->mcg_cap; MCEInjectionParams *params = data;
uint64_t *banks = cenv->mce_banks + 4 * bank; CPUState *cenv = params->env;
uint64_t *banks = cenv->mce_banks + 4 * params->bank;
cpu_synchronize_state(cenv);
/* /*
* If there is an MCE exception being processed, ignore this SRAO MCE * If there is an MCE exception being processed, ignore this SRAO MCE
* unless unconditional injection was requested. * unless unconditional injection was requested.
*/ */
if (!(flags & MCE_INJECT_UNCOND_AO) && !(status & MCI_STATUS_AR) if (!(params->flags & MCE_INJECT_UNCOND_AO)
&& !(params->status & MCI_STATUS_AR)
&& (cenv->mcg_status & MCG_STATUS_MCIP)) { && (cenv->mcg_status & MCG_STATUS_MCIP)) {
return; return;
} }
if (status & MCI_STATUS_UC) {
if (params->status & MCI_STATUS_UC) {
/* /*
* if MSR_MCG_CTL is not all 1s, the uncorrected error * if MSR_MCG_CTL is not all 1s, the uncorrected error
* reporting is disabled * reporting is disabled
*/ */
if ((mcg_cap & MCG_CTL_P) && cenv->mcg_ctl != ~(uint64_t)0) { if ((cenv->mcg_cap & MCG_CTL_P) && cenv->mcg_ctl != ~(uint64_t)0) {
monitor_printf(mon, monitor_printf(params->mon,
"CPU %d: Uncorrected error reporting disabled\n", "CPU %d: Uncorrected error reporting disabled\n",
cenv->cpu_index); cenv->cpu_index);
return; return;
@ -1100,35 +1113,39 @@ qemu_inject_x86_mce(Monitor *mon, CPUState *cenv, int bank, uint64_t status,
* reporting is disabled for the bank * reporting is disabled for the bank
*/ */
if (banks[0] != ~(uint64_t)0) { if (banks[0] != ~(uint64_t)0) {
monitor_printf(mon, "CPU %d: Uncorrected error reporting disabled " monitor_printf(params->mon,
"for bank %d\n", cenv->cpu_index, bank); "CPU %d: Uncorrected error reporting disabled for"
" bank %d\n",
cenv->cpu_index, params->bank);
return; return;
} }
if ((cenv->mcg_status & MCG_STATUS_MCIP) || if ((cenv->mcg_status & MCG_STATUS_MCIP) ||
!(cenv->cr[4] & CR4_MCE_MASK)) { !(cenv->cr[4] & CR4_MCE_MASK)) {
monitor_printf(mon, "CPU %d: Previous MCE still in progress, " monitor_printf(params->mon,
"raising triple fault\n", cenv->cpu_index); "CPU %d: Previous MCE still in progress, raising"
" triple fault\n",
cenv->cpu_index);
qemu_log_mask(CPU_LOG_RESET, "Triple fault\n"); qemu_log_mask(CPU_LOG_RESET, "Triple fault\n");
qemu_system_reset_request(); qemu_system_reset_request();
return; return;
} }
if (banks[1] & MCI_STATUS_VAL) { if (banks[1] & MCI_STATUS_VAL) {
status |= MCI_STATUS_OVER; params->status |= MCI_STATUS_OVER;
} }
banks[2] = addr; banks[2] = params->addr;
banks[3] = misc; banks[3] = params->misc;
cenv->mcg_status = mcg_status; cenv->mcg_status = params->mcg_status;
banks[1] = status; banks[1] = params->status;
cpu_interrupt(cenv, CPU_INTERRUPT_MCE); cpu_interrupt(cenv, CPU_INTERRUPT_MCE);
} else if (!(banks[1] & MCI_STATUS_VAL) } else if (!(banks[1] & MCI_STATUS_VAL)
|| !(banks[1] & MCI_STATUS_UC)) { || !(banks[1] & MCI_STATUS_UC)) {
if (banks[1] & MCI_STATUS_VAL) { if (banks[1] & MCI_STATUS_VAL) {
status |= MCI_STATUS_OVER; params->status |= MCI_STATUS_OVER;
} }
banks[2] = addr; banks[2] = params->addr;
banks[3] = misc; banks[3] = params->misc;
banks[1] = status; banks[1] = params->status;
} else { } else {
banks[1] |= MCI_STATUS_OVER; banks[1] |= MCI_STATUS_OVER;
} }
@ -1138,6 +1155,16 @@ void cpu_x86_inject_mce(Monitor *mon, CPUState *cenv, int bank,
uint64_t status, uint64_t mcg_status, uint64_t addr, uint64_t status, uint64_t mcg_status, uint64_t addr,
uint64_t misc, int flags) uint64_t misc, int flags)
{ {
MCEInjectionParams params = {
.mon = mon,
.env = cenv,
.bank = bank,
.status = status,
.mcg_status = mcg_status,
.addr = addr,
.misc = misc,
.flags = flags,
};
unsigned bank_num = cenv->mcg_cap & 0xff; unsigned bank_num = cenv->mcg_cap & 0xff;
CPUState *env; CPUState *env;
int flag = 0; int flag = 0;
@ -1167,17 +1194,19 @@ void cpu_x86_inject_mce(Monitor *mon, CPUState *cenv, int bank,
kvm_inject_x86_mce(cenv, bank, status, mcg_status, addr, misc, flag); kvm_inject_x86_mce(cenv, bank, status, mcg_status, addr, misc, flag);
} else { } else {
qemu_inject_x86_mce(mon, cenv, bank, status, mcg_status, addr, misc, run_on_cpu(cenv, do_inject_x86_mce, &params);
flags);
if (flags & MCE_INJECT_BROADCAST) { if (flags & MCE_INJECT_BROADCAST) {
params.bank = 1;
params.status = MCI_STATUS_VAL | MCI_STATUS_UC;
params.mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV;
params.addr = 0;
params.misc = 0;
for (env = first_cpu; env != NULL; env = env->next_cpu) { for (env = first_cpu; env != NULL; env = env->next_cpu) {
if (cenv == env) { if (cenv == env) {
continue; continue;
} }
qemu_inject_x86_mce(mon, env, 1, params.env = env;
MCI_STATUS_VAL | MCI_STATUS_UC, run_on_cpu(cenv, do_inject_x86_mce, &params);
MCG_STATUS_MCIP | MCG_STATUS_RIPV, 0, 0,
flags);
} }
} }
} }