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Use qemu_irq between interrupt controller and timers 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2874 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
blueswir1 2007-05-27 16:37:49 +00:00
parent 70c0de96a3
commit d7edfd2702
4 changed files with 39 additions and 41 deletions
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35
hw/slavio_intctl.c
View File

@ -55,6 +55,7 @@ typedef struct SLAVIO_INTCTLState {
#endif
CPUState *cpu_envs[MAX_CPUS];
const uint32_t *intbit_to_level;
uint32_t cputimer_bit;
} SLAVIO_INTCTLState;
#define INTCTL_MAXADDR 0xf
@ -280,7 +281,7 @@ static void slavio_check_interrupts(void *opaque)
* "irq" here is the bit number in the system interrupt register to
* separate serial and keyboard interrupts sharing a level.
*/
void slavio_set_irq(void *opaque, int irq, int level)
static void slavio_set_irq(void *opaque, int irq, int level)
{
SLAVIO_INTCTLState *s = opaque;
@ -302,26 +303,20 @@ void slavio_set_irq(void *opaque, int irq, int level)
}
}
void pic_set_irq_cpu(void *opaque, int irq, int level, unsigned int cpu)
static void slavio_set_timer_irq_cpu(void *opaque, int cpu, int level)
{
SLAVIO_INTCTLState *s = opaque;
DPRINTF("Set cpu %d local irq %d level %d\n", cpu, irq, level);
if (cpu == (unsigned int)-1) {
slavio_set_irq(opaque, irq, level);
DPRINTF("Set cpu %d local level %d\n", cpu, level);
if (!s->cpu_envs[cpu])
return;
if (level) {
s->intreg_pending[cpu] |= s->cputimer_bit;
} else {
s->intreg_pending[cpu] &= ~s->cputimer_bit;
}
if (irq < 32) {
uint32_t pil = s->intbit_to_level[irq];
if (pil > 0) {
if (level) {
s->intreg_pending[cpu] |= 1 << pil;
}
else {
s->intreg_pending[cpu] &= ~(1 << pil);
}
}
}
slavio_check_interrupts(s);
}
@ -371,12 +366,15 @@ static void slavio_intctl_reset(void *opaque)
void slavio_intctl_set_cpu(void *opaque, unsigned int cpu, CPUState *env)
{
SLAVIO_INTCTLState *s = opaque;
s->cpu_envs[cpu] = env;
}
void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
const uint32_t *intbit_to_level,
qemu_irq **irq)
qemu_irq **irq, qemu_irq **cpu_irq,
unsigned int cputimer)
{
int slavio_intctl_io_memory, slavio_intctlm_io_memory, i;
SLAVIO_INTCTLState *s;
@ -398,6 +396,9 @@ void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
register_savevm("slavio_intctl", addr, 1, slavio_intctl_save, slavio_intctl_load, s);
qemu_register_reset(slavio_intctl_reset, s);
*irq = qemu_allocate_irqs(slavio_set_irq, s, 32);
*cpu_irq = qemu_allocate_irqs(slavio_set_timer_irq_cpu, s, MAX_CPUS);
s->cputimer_bit = 1 << s->intbit_to_level[cputimer];
slavio_intctl_reset(s);
return s;
}

24
hw/slavio_timer.c
View File

@ -48,14 +48,12 @@ do { printf("TIMER: " fmt , ##args); } while (0)
*/
typedef struct SLAVIO_TIMERState {
qemu_irq irq;
ptimer_state *timer;
uint32_t count, counthigh, reached;
uint64_t limit;
int irq;
int stopped;
int mode; // 0 = processor, 1 = user, 2 = system
unsigned int cpu;
void *intctl;
} SLAVIO_TIMERState;
#define TIMER_MAXADDR 0x1f
@ -83,7 +81,7 @@ static void slavio_timer_irq(void *opaque)
DPRINTF("callback: count %x%08x\n", s->counthigh, s->count);
s->reached = 0x80000000;
if (s->mode != 1)
pic_set_irq_cpu(s->intctl, s->irq, 1, s->cpu);
qemu_irq_raise(s->irq);
}
static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr)
@ -98,7 +96,7 @@ static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr)
// part of counter (user mode)
if (s->mode != 1) {
// clear irq
pic_set_irq_cpu(s->intctl, s->irq, 0, s->cpu);
qemu_irq_lower(s->irq);
s->reached = 0;
ret = s->limit & 0x7fffffff;
}
@ -145,7 +143,7 @@ static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, uint3
case 0:
// set limit, reset counter
reload = 1;
pic_set_irq_cpu(s->intctl, s->irq, 0, s->cpu);
qemu_irq_lower(s->irq);
// fall through
case 2:
// set limit without resetting counter
@ -172,7 +170,7 @@ static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, uint3
if (s->mode == 0 || s->mode == 1)
s->mode = val & 1;
if (s->mode == 1) {
pic_set_irq_cpu(s->intctl, s->irq, 0, s->cpu);
qemu_irq_lower(s->irq);
s->limit = -1ULL;
}
ptimer_set_limit(s->timer, s->limit >> 9, 1);
@ -201,7 +199,7 @@ static void slavio_timer_save(QEMUFile *f, void *opaque)
qemu_put_be64s(f, &s->limit);
qemu_put_be32s(f, &s->count);
qemu_put_be32s(f, &s->counthigh);
qemu_put_be32s(f, &s->irq);
qemu_put_be32(f, 0); // Was irq
qemu_put_be32s(f, &s->reached);
qemu_put_be32s(f, &s->stopped);
qemu_put_be32s(f, &s->mode);
@ -211,6 +209,7 @@ static void slavio_timer_save(QEMUFile *f, void *opaque)
static int slavio_timer_load(QEMUFile *f, void *opaque, int version_id)
{
SLAVIO_TIMERState *s = opaque;
uint32_t tmp;
if (version_id != 2)
return -EINVAL;
@ -218,7 +217,7 @@ static int slavio_timer_load(QEMUFile *f, void *opaque, int version_id)
qemu_get_be64s(f, &s->limit);
qemu_get_be32s(f, &s->count);
qemu_get_be32s(f, &s->counthigh);
qemu_get_be32s(f, &s->irq);
qemu_get_be32s(f, &tmp); // Was irq
qemu_get_be32s(f, &s->reached);
qemu_get_be32s(f, &s->stopped);
qemu_get_be32s(f, &s->mode);
@ -238,11 +237,10 @@ static void slavio_timer_reset(void *opaque)
ptimer_set_limit(s->timer, s->limit >> 9, 1);
ptimer_run(s->timer, 0);
s->stopped = 1;
slavio_timer_irq(s);
qemu_irq_lower(s->irq);
}
void slavio_timer_init(target_phys_addr_t addr, int irq, int mode,
unsigned int cpu, void *intctl)
void slavio_timer_init(target_phys_addr_t addr, qemu_irq irq, int mode)
{
int slavio_timer_io_memory;
SLAVIO_TIMERState *s;
@ -253,11 +251,9 @@ void slavio_timer_init(target_phys_addr_t addr, int irq, int mode,
return;
s->irq = irq;
s->mode = mode;
s->cpu = cpu;
bh = qemu_bh_new(slavio_timer_irq, s);
s->timer = ptimer_init(bh);
ptimer_set_period(s->timer, 500ULL);
s->intctl = intctl;
slavio_timer_io_memory = cpu_register_io_memory(0, slavio_timer_mem_read,
slavio_timer_mem_write, s);

14
hw/sun4m.c
View File

@ -56,7 +56,7 @@ struct hwdef {
long vram_size, nvram_size;
// IRQ numbers are not PIL ones, but master interrupt controller register
// bit numbers
int intctl_g_intr, esp_irq, le_irq, cpu_irq, clock_irq, clock1_irq;
int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq;
int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq;
int machine_id; // For NVRAM
uint32_t intbit_to_level[32];
@ -264,7 +264,8 @@ static void sun4m_hw_init(const struct hwdef *hwdef, int ram_size,
unsigned int i;
void *iommu, *espdma, *ledma, *main_esp;
const sparc_def_t *def;
qemu_irq *slavio_irq, *espdma_irq, *ledma_irq;
qemu_irq *slavio_irq, *slavio_cpu_irq,
*espdma_irq, *ledma_irq;
/* init CPUs */
sparc_find_by_name(cpu_model, &def);
@ -291,7 +292,8 @@ static void sun4m_hw_init(const struct hwdef *hwdef, int ram_size,
slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
hwdef->intctl_base + 0x10000ULL,
&hwdef->intbit_to_level[0],
&slavio_irq);
&slavio_irq, &slavio_cpu_irq,
hwdef->clock_irq);
for(i = 0; i < smp_cpus; i++) {
slavio_intctl_set_cpu(slavio_intctl, i, envs[i]);
}
@ -320,10 +322,10 @@ static void sun4m_hw_init(const struct hwdef *hwdef, int ram_size,
for (i = 0; i < MAX_CPUS; i++) {
slavio_timer_init(hwdef->counter_base +
(target_phys_addr_t)(i * TARGET_PAGE_SIZE),
hwdef->clock_irq, 0, i, slavio_intctl);
slavio_cpu_irq[i], 0);
}
slavio_timer_init(hwdef->counter_base + 0x10000ULL, hwdef->clock1_irq, 2,
(unsigned int)-1, slavio_intctl);
slavio_timer_init(hwdef->counter_base + 0x10000ULL,
slavio_irq[hwdef->clock1_irq], 2);
slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq]);
// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
// Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device

7
vl.h
View File

@ -1230,10 +1230,10 @@ void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
int depth);
/* slavio_intctl.c */
void pic_set_irq_cpu(void *opaque, int irq, int level, unsigned int cpu);
void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
const uint32_t *intbit_to_level,
qemu_irq **irq);
qemu_irq **irq, qemu_irq **cpu_irq,
unsigned int cputimer);
void slavio_intctl_set_cpu(void *opaque, unsigned int cpu, CPUState *env);
void slavio_pic_info(void *opaque);
void slavio_irq_info(void *opaque);
@ -1247,8 +1247,7 @@ int load_aout(const char *filename, uint8_t *addr);
int load_uboot(const char *filename, target_ulong *ep, int *is_linux);
/* slavio_timer.c */
void slavio_timer_init(target_phys_addr_t addr, int irq, int mode,
unsigned int cpu, void *intctl);
void slavio_timer_init(target_phys_addr_t addr, qemu_irq irq, int mode);
/* slavio_serial.c */
SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq,