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Switch bc1any* instructions off if no MIPS-3D is implemented. 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3426 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths 2007-10-23 13:15:33 +00:00
parent b46a8906b3
commit d8a5950a62
1 changed files with 9 additions and 1 deletions
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10
target-mips/translate.c
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@ -749,6 +749,12 @@ static always_inline void check_cp1_64bitmode(DisasContext *ctx)
generate_exception(ctx, EXCP_RI); generate_exception(ctx, EXCP_RI);
} }
static always_inline void check_cp1_3d(CPUState *env, DisasContext *ctx)
{
if (unlikely(!(env->fpu->fcr0 & (1 << FCR0_3D))))
generate_exception(ctx, EXCP_RI);
}
/* /*
* Verify if floating point register is valid; an operation is not defined * Verify if floating point register is valid; an operation is not defined
* if bit 0 of any register specification is set and the FR bit in the * if bit 0 of any register specification is set and the FR bit in the
@ -6328,9 +6334,11 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
gen_cp1(ctx, op1, rt, rd); gen_cp1(ctx, op1, rt, rd);
break; break;
#endif #endif
case OPC_BC1:
case OPC_BC1ANY2: case OPC_BC1ANY2:
case OPC_BC1ANY4: case OPC_BC1ANY4:
check_cp1_3d(env, ctx);
/* fall through */
case OPC_BC1:
gen_compute_branch1(env, ctx, MASK_BC1(ctx->opcode), gen_compute_branch1(env, ctx, MASK_BC1(ctx->opcode),
(rt >> 2) & 0x7, imm << 2); (rt >> 2) & 0x7, imm << 2);
return; return;