mirror of https://gitee.com/openkylin/qemu.git
pc: acpi-build: create CPU hotplug IO region dynamically
it replaces a static complied in DSDT MMIO region for CPU hotplug with one created at runtime leaving only truly static CPU hotplug related ASL bits in DSDT. It also puts CPU_HOTPLUG_RESOURCE_DEVICE into PCI0 scope and reserves resources from it, preparing for dropping manual hole punching in PCI0._CRS. Later it also would make easier to reuse current ACPI CPU hotplug on other targets. Also later it would be possible to move remaining CPU hotplug ASL methods into build_ssdt() and add all CPU hotplug related AML into SSDT only when CPU hotplug is enabled, further reducing ACPI tables blob if CPU hotplug isn't used. impl. detail: Windows XP can't handle /BSODs/ OperationRegion declaration in DSDT when variable from SSDT is used for specifying its address/length and also when Field declared in DSDT with OperationRegion from SSDT if DSDT is being parsed before SSDT. But it works just fine when referencing named fields from another table. Hence OperationRegion and Field declaration are moved to SSDT to make XP based editions work. PS: Later Windows editions seem to be fine with above conditions. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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@ -101,6 +101,8 @@ typedef struct AcpiPmInfo {
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uint32_t gpe0_blk;
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uint32_t gpe0_blk_len;
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uint32_t io_base;
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uint16_t cpu_hp_io_base;
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uint16_t cpu_hp_io_len;
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} AcpiPmInfo;
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typedef struct AcpiMiscInfo {
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@ -176,12 +178,15 @@ static void acpi_get_pm_info(AcpiPmInfo *pm)
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if (piix) {
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obj = piix;
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pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
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}
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if (lpc) {
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obj = lpc;
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pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
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}
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assert(obj);
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pm->cpu_hp_io_len = ACPI_GPE_PROC_LEN;
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/* Fill in optional s3/s4 related properties */
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o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
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if (o) {
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@ -995,6 +1000,28 @@ build_ssdt(GArray *table_data, GArray *linker,
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sb_scope = aml_scope("_SB");
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{
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/* create PCI0.PRES device and its _CRS to reserve CPU hotplug MMIO */
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dev = aml_device("PCI0." stringify(CPU_HOTPLUG_RESOURCE_DEVICE));
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aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
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aml_append(dev,
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aml_name_decl("_UID", aml_string("CPU Hotplug resources"))
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);
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/* device present, functioning, decoding, not shown in UI */
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aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
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crs = aml_resource_template();
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aml_append(crs,
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aml_io(aml_decode16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1,
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pm->cpu_hp_io_len)
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);
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aml_append(dev, aml_name_decl("_CRS", crs));
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aml_append(sb_scope, dev);
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/* declare CPU hotplug MMIO region and PRS field to access it */
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aml_append(sb_scope, aml_operation_region(
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"PRST", aml_system_io, pm->cpu_hp_io_base, pm->cpu_hp_io_len));
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field = aml_field("PRST", aml_byte_acc);
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aml_append(field, aml_named_field("PRS", 256));
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aml_append(sb_scope, field);
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/* build Processor object for each processor */
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for (i = 0; i < acpi_cpus; i++) {
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dev = aml_processor(i, 0, 0, "CP%.02X", i);
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@ -16,12 +16,12 @@
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/****************************************************************
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* CPU hotplug
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****************************************************************/
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#define CPU_HOTPLUG_RESOURCE_DEVICE PRES
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Scope(\_SB) {
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/* Objects filled in by run-time generated SSDT */
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External(NTFY, MethodObj)
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External(CPON, PkgObj)
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External(PRS, FieldUnitObj)
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/* Methods called by run-time generated SSDT Processor objects */
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Method(CPMA, 1, NotSerialized) {
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@ -54,10 +54,6 @@ Scope(\_SB) {
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}
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#define CPU_STATUS_LEN ACPI_GPE_PROC_LEN
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OperationRegion(PRST, SystemIO, CPU_STATUS_BASE, CPU_STATUS_LEN)
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Field(PRST, ByteAcc, NoLock, Preserve) {
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PRS, 256
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}
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Method(PRSC, 0) {
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// Local5 = active cpu bitmap
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Store(PRS, Local5)
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@ -91,15 +87,4 @@ Scope(\_SB) {
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Increment(Local0)
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}
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}
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Device(CPU_HOTPLUG_RESOURCE_DEVICE) {
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Name(_HID, EisaId("PNP0A06"))
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Name(_UID, "CPU hotplug resources")
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Name(_CRS, ResourceTemplate() {
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IO(Decode16, CPU_STATUS_BASE, CPU_STATUS_BASE, 0, CPU_STATUS_LEN)
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})
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Name(_STA, 0xB) /* present, functioning, decoding, not shown in UI */
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}
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}
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@ -28,6 +28,7 @@
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#define ICH9_CPU_HOTPLUG_IO_BASE 0x0CD8
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#define PIIX4_CPU_HOTPLUG_IO_BASE 0xaf00
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#define CPU_HOTPLUG_RESOURCE_DEVICE PRES
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#define ACPI_MEMORY_HOTPLUG_IO_LEN 24
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#define ACPI_MEMORY_HOTPLUG_BASE 0x0a00
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