mirror of https://gitee.com/openkylin/qemu.git
target-arm: A64: Add SIMD ld/st single
Implement the SIMD ld/st single structure instructions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Peter Maydell
parent
72430bf5eb
commit
df54e47d2b
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@ -2087,10 +2087,150 @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
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tcg_temp_free_i64(tcg_addr);
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}
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/* AdvSIMD load/store single structure */
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/* C3.3.3 AdvSIMD load/store single structure
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*
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* 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
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* +---+---+---------------+-----+-----------+-----+---+------+------+------+
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* | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
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* +---+---+---------------+-----+-----------+-----+---+------+------+------+
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*
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* C3.3.4 AdvSIMD load/store single structure (post-indexed)
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*
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* 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
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* +---+---+---------------+-----+-----------+-----+---+------+------+------+
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* | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
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* +---+---+---------------+-----+-----------+-----+---+------+------+------+
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*
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* Rt: first (or only) SIMD&FP register to be transferred
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* Rn: base address or SP
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* Rm (post-index only): post-index register (when !31) or size dependent #imm
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* index = encoded in Q:S:size dependent on size
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*
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* lane_size = encoded in R, opc
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* transfer width = encoded in opc, S, size
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*/
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static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
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{
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unsupported_encoding(s, insn);
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int rt = extract32(insn, 0, 5);
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int rn = extract32(insn, 5, 5);
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int size = extract32(insn, 10, 2);
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int S = extract32(insn, 12, 1);
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int opc = extract32(insn, 13, 3);
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int R = extract32(insn, 21, 1);
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int is_load = extract32(insn, 22, 1);
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int is_postidx = extract32(insn, 23, 1);
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int is_q = extract32(insn, 30, 1);
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int scale = extract32(opc, 1, 2);
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int selem = (extract32(opc, 0, 1) << 1 | R) + 1;
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bool replicate = false;
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int index = is_q << 3 | S << 2 | size;
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int ebytes, xs;
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TCGv_i64 tcg_addr, tcg_rn;
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switch (scale) {
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case 3:
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if (!is_load || S) {
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unallocated_encoding(s);
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return;
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}
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scale = size;
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replicate = true;
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break;
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case 0:
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break;
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case 1:
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if (extract32(size, 0, 1)) {
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unallocated_encoding(s);
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return;
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}
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index >>= 1;
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break;
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case 2:
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if (extract32(size, 1, 1)) {
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unallocated_encoding(s);
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return;
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}
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if (!extract32(size, 0, 1)) {
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index >>= 2;
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} else {
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if (S) {
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unallocated_encoding(s);
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return;
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}
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index >>= 3;
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scale = 3;
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}
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break;
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default:
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g_assert_not_reached();
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}
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ebytes = 1 << scale;
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if (rn == 31) {
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gen_check_sp_alignment(s);
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}
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tcg_rn = cpu_reg_sp(s, rn);
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tcg_addr = tcg_temp_new_i64();
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tcg_gen_mov_i64(tcg_addr, tcg_rn);
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for (xs = 0; xs < selem; xs++) {
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if (replicate) {
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/* Load and replicate to all elements */
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uint64_t mulconst;
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TCGv_i64 tcg_tmp = tcg_temp_new_i64();
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tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr,
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get_mem_index(s), MO_TE + scale);
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switch (scale) {
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case 0:
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mulconst = 0x0101010101010101ULL;
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break;
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case 1:
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mulconst = 0x0001000100010001ULL;
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break;
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case 2:
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mulconst = 0x0000000100000001ULL;
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break;
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case 3:
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mulconst = 0;
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break;
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default:
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g_assert_not_reached();
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}
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if (mulconst) {
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tcg_gen_muli_i64(tcg_tmp, tcg_tmp, mulconst);
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}
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write_vec_element(s, tcg_tmp, rt, 0, MO_64);
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if (is_q) {
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write_vec_element(s, tcg_tmp, rt, 1, MO_64);
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} else {
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clear_vec_high(s, rt);
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}
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tcg_temp_free_i64(tcg_tmp);
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} else {
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/* Load/store one element per register */
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if (is_load) {
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do_vec_ld(s, rt, index, tcg_addr, MO_TE + scale);
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} else {
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do_vec_st(s, rt, index, tcg_addr, MO_TE + scale);
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}
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}
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tcg_gen_addi_i64(tcg_addr, tcg_addr, ebytes);
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rt = (rt + 1) % 32;
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}
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if (is_postidx) {
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int rm = extract32(insn, 16, 5);
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if (rm == 31) {
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tcg_gen_mov_i64(tcg_rn, tcg_addr);
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} else {
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tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm));
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}
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}
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tcg_temp_free_i64(tcg_addr);
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}
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/* C3.3 Loads and stores */
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