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SPARC64: Implement stfa/stdfa/stqfa instrcutions properly 

This patch implements sparcv9 stfa/stdfa/stqfa instructions
with non block-store ASIs.

Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Tsuneo Saito 2011-07-14 18:41:38 +09:00 committed by Blue Swirl
parent 8872eb4f56
commit e1ef36c4a3
2 changed files with 11 additions and 6 deletions
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15
target-sparc/op_helper.c
View File

@ -3396,6 +3396,7 @@ void helper_stf_asi(target_ulong addr, int asi, int size, int rd)
{ {
unsigned int i; unsigned int i;
target_ulong val = 0; target_ulong val = 0;
CPU_DoubleU u;
helper_check_align(addr, 3); helper_check_align(addr, 3);
addr = asi_address_mask(env, asi, addr); addr = asi_address_mask(env, asi, addr);
@ -3440,16 +3441,22 @@ void helper_stf_asi(target_ulong addr, int asi, int size, int rd)
switch(size) { switch(size) {
default: default:
case 4: case 4:
val = *((uint32_t *)&env->fpr[rd]); helper_st_asi(addr, *(uint32_t *)&env->fpr[rd], asi, size);
break; break;
case 8: case 8:
val = *((int64_t *)&DT0); u.l.upper = *(uint32_t *)&env->fpr[rd++];
u.l.lower = *(uint32_t *)&env->fpr[rd++];
helper_st_asi(addr, u.ll, asi, size);
break; break;
case 16: case 16:
// XXX u.l.upper = *(uint32_t *)&env->fpr[rd++];
u.l.lower = *(uint32_t *)&env->fpr[rd++];
helper_st_asi(addr, u.ll, asi, 8);
u.l.upper = *(uint32_t *)&env->fpr[rd++];
u.l.lower = *(uint32_t *)&env->fpr[rd++];
helper_st_asi(addr + 8, u.ll, asi, 8);
break; break;
} }
helper_st_asi(addr, val, asi, size);
} }
target_ulong helper_cas_asi(target_ulong addr, target_ulong val1, target_ulong helper_cas_asi(target_ulong addr, target_ulong val1,

2
target-sparc/translate.c
View File

@ -4742,12 +4742,10 @@ static void disas_sparc_insn(DisasContext * dc)
r_const = tcg_const_i32(7); r_const = tcg_const_i32(7);
gen_helper_check_align(cpu_addr, r_const); gen_helper_check_align(cpu_addr, r_const);
tcg_temp_free_i32(r_const); tcg_temp_free_i32(r_const);
gen_op_load_fpr_QT0(QFPREG(rd));
gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd)); gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
} }
break; break;
case 0x37: /* V9 stdfa */ case 0x37: /* V9 stdfa */
gen_op_load_fpr_DT0(DFPREG(rd));
gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd)); gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
break; break;
case 0x3c: /* V9 casa */ case 0x3c: /* V9 casa */