mirror of https://gitee.com/openkylin/qemu.git
correct split between helper.c and op_helper.c - cosmetics
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1505 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
parent
fdabc366bd
commit
e37e863f5e
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@ -240,174 +240,6 @@ enum {
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EXCP_FLUSH = 0x109,
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};
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/* MIPS opcodes */
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#define EXT_SPECIAL 0x100
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#define EXT_SPECIAL2 0x200
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#define EXT_REGIMM 0x300
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#define EXT_CP0 0x400
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#define EXT_CP1 0x500
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#define EXT_CP2 0x600
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#define EXT_CP3 0x700
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enum {
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/* indirect opcode tables */
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OPC_SPECIAL = 0x00,
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OPC_BREGIMM = 0x01,
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OPC_CP0 = 0x10,
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OPC_CP1 = 0x11,
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OPC_CP2 = 0x12,
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OPC_CP3 = 0x13,
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OPC_SPECIAL2 = 0x1C,
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/* arithmetic with immediate */
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OPC_ADDI = 0x08,
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OPC_ADDIU = 0x09,
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OPC_SLTI = 0x0A,
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OPC_SLTIU = 0x0B,
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OPC_ANDI = 0x0C,
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OPC_ORI = 0x0D,
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OPC_XORI = 0x0E,
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OPC_LUI = 0x0F,
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/* Jump and branches */
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OPC_J = 0x02,
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OPC_JAL = 0x03,
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OPC_BEQ = 0x04, /* Unconditional if rs = rt = 0 (B) */
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OPC_BEQL = 0x14,
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OPC_BNE = 0x05,
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OPC_BNEL = 0x15,
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OPC_BLEZ = 0x06,
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OPC_BLEZL = 0x16,
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OPC_BGTZ = 0x07,
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OPC_BGTZL = 0x17,
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OPC_JALX = 0x1D, /* MIPS 16 only */
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/* Load and stores */
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OPC_LB = 0x20,
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OPC_LH = 0x21,
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OPC_LWL = 0x22,
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OPC_LW = 0x23,
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OPC_LBU = 0x24,
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OPC_LHU = 0x25,
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OPC_LWR = 0x26,
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OPC_SB = 0x28,
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OPC_SH = 0x29,
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OPC_SWL = 0x2A,
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OPC_SW = 0x2B,
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OPC_SWR = 0x2E,
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OPC_LL = 0x30,
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OPC_SC = 0x38,
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/* Floating point load/store */
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OPC_LWC1 = 0x31,
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OPC_LWC2 = 0x32,
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OPC_LDC1 = 0x35,
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OPC_LDC2 = 0x36,
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OPC_SWC1 = 0x39,
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OPC_SWC2 = 0x3A,
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OPC_SDC1 = 0x3D,
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OPC_SDC2 = 0x3E,
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/* Cache and prefetch */
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OPC_CACHE = 0x2F,
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OPC_PREF = 0x33,
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};
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/* MIPS special opcodes */
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enum {
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/* Shifts */
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OPC_SLL = 0x00 | EXT_SPECIAL,
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/* NOP is SLL r0, r0, 0 */
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/* SSNOP is SLL r0, r0, 1 */
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OPC_SRL = 0x02 | EXT_SPECIAL,
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OPC_SRA = 0x03 | EXT_SPECIAL,
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OPC_SLLV = 0x04 | EXT_SPECIAL,
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OPC_SRLV = 0x06 | EXT_SPECIAL,
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OPC_SRAV = 0x07 | EXT_SPECIAL,
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/* Multiplication / division */
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OPC_MULT = 0x18 | EXT_SPECIAL,
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OPC_MULTU = 0x19 | EXT_SPECIAL,
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OPC_DIV = 0x1A | EXT_SPECIAL,
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OPC_DIVU = 0x1B | EXT_SPECIAL,
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/* 2 registers arithmetic / logic */
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OPC_ADD = 0x20 | EXT_SPECIAL,
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OPC_ADDU = 0x21 | EXT_SPECIAL,
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OPC_SUB = 0x22 | EXT_SPECIAL,
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OPC_SUBU = 0x23 | EXT_SPECIAL,
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OPC_AND = 0x24 | EXT_SPECIAL,
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OPC_OR = 0x25 | EXT_SPECIAL,
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OPC_XOR = 0x26 | EXT_SPECIAL,
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OPC_NOR = 0x27 | EXT_SPECIAL,
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OPC_SLT = 0x2A | EXT_SPECIAL,
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OPC_SLTU = 0x2B | EXT_SPECIAL,
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/* Jumps */
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OPC_JR = 0x08 | EXT_SPECIAL,
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OPC_JALR = 0x09 | EXT_SPECIAL,
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/* Traps */
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OPC_TGE = 0x30 | EXT_SPECIAL,
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OPC_TGEU = 0x31 | EXT_SPECIAL,
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OPC_TLT = 0x32 | EXT_SPECIAL,
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OPC_TLTU = 0x33 | EXT_SPECIAL,
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OPC_TEQ = 0x34 | EXT_SPECIAL,
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OPC_TNE = 0x36 | EXT_SPECIAL,
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/* HI / LO registers load & stores */
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OPC_MFHI = 0x10 | EXT_SPECIAL,
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OPC_MTHI = 0x11 | EXT_SPECIAL,
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OPC_MFLO = 0x12 | EXT_SPECIAL,
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OPC_MTLO = 0x13 | EXT_SPECIAL,
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/* Conditional moves */
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OPC_MOVZ = 0x0A | EXT_SPECIAL,
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OPC_MOVN = 0x0B | EXT_SPECIAL,
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OPC_MOVCI = 0x01 | EXT_SPECIAL,
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/* Special */
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OPC_PMON = 0x05 | EXT_SPECIAL,
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OPC_SYSCALL = 0x0C | EXT_SPECIAL,
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OPC_BREAK = 0x0D | EXT_SPECIAL,
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OPC_SYNC = 0x0F | EXT_SPECIAL,
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};
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enum {
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/* Mutiply & xxx operations */
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OPC_MADD = 0x00 | EXT_SPECIAL2,
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OPC_MADDU = 0x01 | EXT_SPECIAL2,
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OPC_MUL = 0x02 | EXT_SPECIAL2,
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OPC_MSUB = 0x04 | EXT_SPECIAL2,
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OPC_MSUBU = 0x05 | EXT_SPECIAL2,
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/* Misc */
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OPC_CLZ = 0x20 | EXT_SPECIAL2,
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OPC_CLO = 0x21 | EXT_SPECIAL2,
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/* Special */
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OPC_SDBBP = 0x3F | EXT_SPECIAL2,
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};
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/* Branch REGIMM */
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enum {
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OPC_BLTZ = 0x00 | EXT_REGIMM,
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OPC_BLTZL = 0x02 | EXT_REGIMM,
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OPC_BGEZ = 0x01 | EXT_REGIMM,
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OPC_BGEZL = 0x03 | EXT_REGIMM,
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OPC_BLTZAL = 0x10 | EXT_REGIMM,
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OPC_BLTZALL = 0x12 | EXT_REGIMM,
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OPC_BGEZAL = 0x11 | EXT_REGIMM,
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OPC_BGEZALL = 0x13 | EXT_REGIMM,
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OPC_TGEI = 0x08 | EXT_REGIMM,
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OPC_TGEIU = 0x09 | EXT_REGIMM,
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OPC_TLTI = 0x0A | EXT_REGIMM,
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OPC_TLTIU = 0x0B | EXT_REGIMM,
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OPC_TEQI = 0x0C | EXT_REGIMM,
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OPC_TNEI = 0x0E | EXT_REGIMM,
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};
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enum {
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/* Coprocessor 0 (MMU) */
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OPC_MFC0 = 0x00 | EXT_CP0,
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OPC_MTC0 = 0x04 | EXT_CP0,
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OPC_TLBR = 0x01 | EXT_CP0,
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OPC_TLBWI = 0x02 | EXT_CP0,
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OPC_TLBWR = 0x06 | EXT_CP0,
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OPC_TLBP = 0x08 | EXT_CP0,
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OPC_ERET = 0x18 | EXT_CP0,
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OPC_DERET = 0x1F | EXT_CP0,
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OPC_WAIT = 0x20 | EXT_CP0,
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};
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int cpu_mips_exec(CPUMIPSState *s);
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CPUMIPSState *cpu_mips_init(void);
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uint32_t cpu_mips_get_clock (void);
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@ -19,27 +19,15 @@ typedef uint32_t host_uint_t;
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register host_uint_t T0 asm(AREG1);
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register host_uint_t T1 asm(AREG2);
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register host_uint_t T2 asm(AREG3);
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register host_int_t Ts0 asm(AREG1);
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register host_int_t Ts1 asm(AREG2);
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register host_int_t Ts2 asm(AREG3);
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#define PARAM(n) ((uint32_t)PARAM##n)
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#define SPARAM(n) ((int32_t)PARAM##n)
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#if defined (USE_HOST_FLOAT_REGS)
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register double FT0 asm(FREG0);
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register double FT1 asm(FREG1);
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register double FT2 asm(FREG2);
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register float FTS0 asm(FREG0);
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register float FTS1 asm(FREG1);
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register float FTS2 asm(FREG2);
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#else
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#define FT0 (env->ft0.d)
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#define FT1 (env->ft1.d)
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#define FT2 (env->ft2.d)
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#define FTS0 (env->ft0.f)
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#define FTS1 (env->ft1.f)
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#define FTS2 (env->ft2.f)
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#endif
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#if defined (DEBUG_OP)
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@ -17,7 +17,16 @@
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "exec.h"
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#include <stdarg.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <inttypes.h>
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#include <signal.h>
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#include <assert.h>
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#include "cpu.h"
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#include "exec-all.h"
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/* MIPS32 4K MMU emulation */
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#ifdef MIPS_USES_R4K_TLB
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@ -142,57 +151,10 @@ target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
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return -1;
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return phys_addr;
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}
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#endif
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#if !defined(CONFIG_USER_ONLY)
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#define MMUSUFFIX _mmu
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#define GETPC() (__builtin_return_address(0))
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#define SHIFT 0
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#include "softmmu_template.h"
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#define SHIFT 1
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#include "softmmu_template.h"
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#define SHIFT 2
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#include "softmmu_template.h"
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#define SHIFT 3
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#include "softmmu_template.h"
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void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr)
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{
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TranslationBlock *tb;
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CPUState *saved_env;
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unsigned long pc;
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int ret;
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/* XXX: hack to restore env in all cases, even if not called from
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generated code */
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saved_env = env;
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env = cpu_single_env;
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ret = cpu_mips_handle_mmu_fault(env, addr, is_write, is_user, 1);
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if (ret) {
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if (retaddr) {
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/* now we have a real cpu fault */
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pc = (unsigned long)retaddr;
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tb = tb_find_pc(pc);
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if (tb) {
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/* the PC is inside the translated code. It means that we have
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a virtual CPU fault */
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cpu_restore_state(tb, env, pc, NULL);
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}
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}
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do_raise_exception_err(env->exception_index, env->error_code);
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}
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env = saved_env;
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}
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void cpu_mips_init_mmu (CPUState *env)
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{
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}
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#endif /* !defined(CONFIG_USER_ONLY) */
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int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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@ -29,7 +29,6 @@ void cpu_loop_exit(void)
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longjmp(env->jmp_env, 1);
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}
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__attribute__ (( regparm(2) ))
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void do_raise_exception_err (uint32_t exception, int error_code)
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{
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#if 1
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@ -42,7 +41,6 @@ void do_raise_exception_err (uint32_t exception, int error_code)
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cpu_loop_exit();
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}
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__attribute__ (( regparm(1) ))
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void do_raise_exception (uint32_t exception)
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{
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do_raise_exception_err(exception, 0);
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@ -117,7 +115,6 @@ void do_msubu (void)
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#endif
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/* CP0 helpers */
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__attribute__ (( regparm(2) ))
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void do_mfc0 (int reg, int sel)
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{
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const unsigned char *rn;
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@ -267,12 +264,10 @@ void do_mfc0 (int reg, int sel)
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return;
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}
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__attribute__ (( regparm(2) ))
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void do_mtc0 (int reg, int sel)
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{
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const unsigned char *rn;
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uint32_t val, old, mask;
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int i, raise;
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if (sel != 0 && reg != 16 && reg != 28) {
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val = -1;
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@ -379,11 +374,14 @@ void do_mtc0 (int reg, int sel)
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old = env->CP0_Cause;
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env->CP0_Cause = val;
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#if 0
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/* Check if we ever asserted a software IRQ */
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for (i = 0; i < 2; i++) {
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mask = 0x100 << i;
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if ((val & mask) & !(old & mask))
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mips_set_irq(i);
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{
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int i;
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/* Check if we ever asserted a software IRQ */
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for (i = 0; i < 2; i++) {
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mask = 0x100 << i;
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if ((val & mask) & !(old & mask))
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mips_set_irq(i);
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}
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}
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#endif
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rn = "Cause";
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@ -486,7 +484,6 @@ void do_mtc0 (int reg, int sel)
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/* TLB management */
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#if defined(MIPS_USES_R4K_TLB)
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__attribute__ (( regparm(1) ))
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static void invalidate_tb (int idx)
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{
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tlb_t *tlb;
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@ -505,7 +502,6 @@ static void invalidate_tb (int idx)
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}
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}
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__attribute__ (( regparm(1) ))
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static void fill_tb (int idx)
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{
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tlb_t *tlb;
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@ -584,7 +580,6 @@ void do_tlbr (void)
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}
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#endif
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__attribute__ (( regparm(1) ))
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void op_dump_ldst (const unsigned char *func)
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{
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if (loglevel)
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@ -608,7 +603,6 @@ void debug_eret (void)
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}
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}
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__attribute__ (( regparm(1) ))
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void do_pmon (int function)
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{
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function /= 2;
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@ -634,3 +628,50 @@ void do_pmon (int function)
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break;
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}
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}
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#if !defined(CONFIG_USER_ONLY)
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#define MMUSUFFIX _mmu
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#define GETPC() (__builtin_return_address(0))
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#define SHIFT 0
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#include "softmmu_template.h"
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#define SHIFT 1
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#include "softmmu_template.h"
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#define SHIFT 2
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#include "softmmu_template.h"
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#define SHIFT 3
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#include "softmmu_template.h"
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void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr)
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{
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TranslationBlock *tb;
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CPUState *saved_env;
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unsigned long pc;
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int ret;
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/* XXX: hack to restore env in all cases, even if not called from
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generated code */
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saved_env = env;
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env = cpu_single_env;
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ret = cpu_mips_handle_mmu_fault(env, addr, is_write, is_user, 1);
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if (ret) {
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if (retaddr) {
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/* now we have a real cpu fault */
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pc = (unsigned long)retaddr;
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tb = tb_find_pc(pc);
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if (tb) {
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/* the PC is inside the translated code. It means that we have
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a virtual CPU fault */
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cpu_restore_state(tb, env, pc, NULL);
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}
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}
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do_raise_exception_err(env->exception_index, env->error_code);
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}
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env = saved_env;
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}
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#endif
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@ -43,6 +43,174 @@ static uint32_t *gen_opparam_ptr;
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#include "gen-op.h"
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/* MIPS opcodes */
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#define EXT_SPECIAL 0x100
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#define EXT_SPECIAL2 0x200
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#define EXT_REGIMM 0x300
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#define EXT_CP0 0x400
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#define EXT_CP1 0x500
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#define EXT_CP2 0x600
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#define EXT_CP3 0x700
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enum {
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/* indirect opcode tables */
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OPC_SPECIAL = 0x00,
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OPC_BREGIMM = 0x01,
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OPC_CP0 = 0x10,
|
||||
OPC_CP1 = 0x11,
|
||||
OPC_CP2 = 0x12,
|
||||
OPC_CP3 = 0x13,
|
||||
OPC_SPECIAL2 = 0x1C,
|
||||
/* arithmetic with immediate */
|
||||
OPC_ADDI = 0x08,
|
||||
OPC_ADDIU = 0x09,
|
||||
OPC_SLTI = 0x0A,
|
||||
OPC_SLTIU = 0x0B,
|
||||
OPC_ANDI = 0x0C,
|
||||
OPC_ORI = 0x0D,
|
||||
OPC_XORI = 0x0E,
|
||||
OPC_LUI = 0x0F,
|
||||
/* Jump and branches */
|
||||
OPC_J = 0x02,
|
||||
OPC_JAL = 0x03,
|
||||
OPC_BEQ = 0x04, /* Unconditional if rs = rt = 0 (B) */
|
||||
OPC_BEQL = 0x14,
|
||||
OPC_BNE = 0x05,
|
||||
OPC_BNEL = 0x15,
|
||||
OPC_BLEZ = 0x06,
|
||||
OPC_BLEZL = 0x16,
|
||||
OPC_BGTZ = 0x07,
|
||||
OPC_BGTZL = 0x17,
|
||||
OPC_JALX = 0x1D, /* MIPS 16 only */
|
||||
/* Load and stores */
|
||||
OPC_LB = 0x20,
|
||||
OPC_LH = 0x21,
|
||||
OPC_LWL = 0x22,
|
||||
OPC_LW = 0x23,
|
||||
OPC_LBU = 0x24,
|
||||
OPC_LHU = 0x25,
|
||||
OPC_LWR = 0x26,
|
||||
OPC_SB = 0x28,
|
||||
OPC_SH = 0x29,
|
||||
OPC_SWL = 0x2A,
|
||||
OPC_SW = 0x2B,
|
||||
OPC_SWR = 0x2E,
|
||||
OPC_LL = 0x30,
|
||||
OPC_SC = 0x38,
|
||||
/* Floating point load/store */
|
||||
OPC_LWC1 = 0x31,
|
||||
OPC_LWC2 = 0x32,
|
||||
OPC_LDC1 = 0x35,
|
||||
OPC_LDC2 = 0x36,
|
||||
OPC_SWC1 = 0x39,
|
||||
OPC_SWC2 = 0x3A,
|
||||
OPC_SDC1 = 0x3D,
|
||||
OPC_SDC2 = 0x3E,
|
||||
/* Cache and prefetch */
|
||||
OPC_CACHE = 0x2F,
|
||||
OPC_PREF = 0x33,
|
||||
};
|
||||
|
||||
/* MIPS special opcodes */
|
||||
enum {
|
||||
/* Shifts */
|
||||
OPC_SLL = 0x00 | EXT_SPECIAL,
|
||||
/* NOP is SLL r0, r0, 0 */
|
||||
/* SSNOP is SLL r0, r0, 1 */
|
||||
OPC_SRL = 0x02 | EXT_SPECIAL,
|
||||
OPC_SRA = 0x03 | EXT_SPECIAL,
|
||||
OPC_SLLV = 0x04 | EXT_SPECIAL,
|
||||
OPC_SRLV = 0x06 | EXT_SPECIAL,
|
||||
OPC_SRAV = 0x07 | EXT_SPECIAL,
|
||||
/* Multiplication / division */
|
||||
OPC_MULT = 0x18 | EXT_SPECIAL,
|
||||
OPC_MULTU = 0x19 | EXT_SPECIAL,
|
||||
OPC_DIV = 0x1A | EXT_SPECIAL,
|
||||
OPC_DIVU = 0x1B | EXT_SPECIAL,
|
||||
/* 2 registers arithmetic / logic */
|
||||
OPC_ADD = 0x20 | EXT_SPECIAL,
|
||||
OPC_ADDU = 0x21 | EXT_SPECIAL,
|
||||
OPC_SUB = 0x22 | EXT_SPECIAL,
|
||||
OPC_SUBU = 0x23 | EXT_SPECIAL,
|
||||
OPC_AND = 0x24 | EXT_SPECIAL,
|
||||
OPC_OR = 0x25 | EXT_SPECIAL,
|
||||
OPC_XOR = 0x26 | EXT_SPECIAL,
|
||||
OPC_NOR = 0x27 | EXT_SPECIAL,
|
||||
OPC_SLT = 0x2A | EXT_SPECIAL,
|
||||
OPC_SLTU = 0x2B | EXT_SPECIAL,
|
||||
/* Jumps */
|
||||
OPC_JR = 0x08 | EXT_SPECIAL,
|
||||
OPC_JALR = 0x09 | EXT_SPECIAL,
|
||||
/* Traps */
|
||||
OPC_TGE = 0x30 | EXT_SPECIAL,
|
||||
OPC_TGEU = 0x31 | EXT_SPECIAL,
|
||||
OPC_TLT = 0x32 | EXT_SPECIAL,
|
||||
OPC_TLTU = 0x33 | EXT_SPECIAL,
|
||||
OPC_TEQ = 0x34 | EXT_SPECIAL,
|
||||
OPC_TNE = 0x36 | EXT_SPECIAL,
|
||||
/* HI / LO registers load & stores */
|
||||
OPC_MFHI = 0x10 | EXT_SPECIAL,
|
||||
OPC_MTHI = 0x11 | EXT_SPECIAL,
|
||||
OPC_MFLO = 0x12 | EXT_SPECIAL,
|
||||
OPC_MTLO = 0x13 | EXT_SPECIAL,
|
||||
/* Conditional moves */
|
||||
OPC_MOVZ = 0x0A | EXT_SPECIAL,
|
||||
OPC_MOVN = 0x0B | EXT_SPECIAL,
|
||||
|
||||
OPC_MOVCI = 0x01 | EXT_SPECIAL,
|
||||
|
||||
/* Special */
|
||||
OPC_PMON = 0x05 | EXT_SPECIAL,
|
||||
OPC_SYSCALL = 0x0C | EXT_SPECIAL,
|
||||
OPC_BREAK = 0x0D | EXT_SPECIAL,
|
||||
OPC_SYNC = 0x0F | EXT_SPECIAL,
|
||||
};
|
||||
|
||||
enum {
|
||||
/* Mutiply & xxx operations */
|
||||
OPC_MADD = 0x00 | EXT_SPECIAL2,
|
||||
OPC_MADDU = 0x01 | EXT_SPECIAL2,
|
||||
OPC_MUL = 0x02 | EXT_SPECIAL2,
|
||||
OPC_MSUB = 0x04 | EXT_SPECIAL2,
|
||||
OPC_MSUBU = 0x05 | EXT_SPECIAL2,
|
||||
/* Misc */
|
||||
OPC_CLZ = 0x20 | EXT_SPECIAL2,
|
||||
OPC_CLO = 0x21 | EXT_SPECIAL2,
|
||||
/* Special */
|
||||
OPC_SDBBP = 0x3F | EXT_SPECIAL2,
|
||||
};
|
||||
|
||||
/* Branch REGIMM */
|
||||
enum {
|
||||
OPC_BLTZ = 0x00 | EXT_REGIMM,
|
||||
OPC_BLTZL = 0x02 | EXT_REGIMM,
|
||||
OPC_BGEZ = 0x01 | EXT_REGIMM,
|
||||
OPC_BGEZL = 0x03 | EXT_REGIMM,
|
||||
OPC_BLTZAL = 0x10 | EXT_REGIMM,
|
||||
OPC_BLTZALL = 0x12 | EXT_REGIMM,
|
||||
OPC_BGEZAL = 0x11 | EXT_REGIMM,
|
||||
OPC_BGEZALL = 0x13 | EXT_REGIMM,
|
||||
OPC_TGEI = 0x08 | EXT_REGIMM,
|
||||
OPC_TGEIU = 0x09 | EXT_REGIMM,
|
||||
OPC_TLTI = 0x0A | EXT_REGIMM,
|
||||
OPC_TLTIU = 0x0B | EXT_REGIMM,
|
||||
OPC_TEQI = 0x0C | EXT_REGIMM,
|
||||
OPC_TNEI = 0x0E | EXT_REGIMM,
|
||||
};
|
||||
|
||||
enum {
|
||||
/* Coprocessor 0 (MMU) */
|
||||
OPC_MFC0 = 0x00 | EXT_CP0,
|
||||
OPC_MTC0 = 0x04 | EXT_CP0,
|
||||
OPC_TLBR = 0x01 | EXT_CP0,
|
||||
OPC_TLBWI = 0x02 | EXT_CP0,
|
||||
OPC_TLBWR = 0x06 | EXT_CP0,
|
||||
OPC_TLBP = 0x08 | EXT_CP0,
|
||||
OPC_ERET = 0x18 | EXT_CP0,
|
||||
OPC_DERET = 0x1F | EXT_CP0,
|
||||
OPC_WAIT = 0x20 | EXT_CP0,
|
||||
};
|
||||
|
||||
const unsigned char *regnames[] =
|
||||
{ "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
|
||||
"t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
|
||||
|
|
|
|||
Loading…
Reference in New Issue