mirror of https://gitee.com/openkylin/qemu.git
PPC64: Fix timebase
On PPC we have a 64-bit time base. Usually (PPC32) this is accessed using two separate 32 bit SPR accesses to SPR_TBU and SPR_TBL. On PPC64 the SPR_TBL register acts as 64 bit though, so we get the full 64 bits as return value. If we only take the lower ones, fine. But Linux wants to see all 64 bits or it breaks. This patch makes PPC64 Linux work even after TB crossed the 32-bit boundary, which usually happened a few seconds after bootup. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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@ -82,9 +82,9 @@ static inline uint64_t cpu_ppc_get_tb (CPUState *env)
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return 0;
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return 0;
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}
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}
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uint32_t cpu_ppc_load_tbl (CPUState *env)
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uint64_t cpu_ppc_load_tbl (CPUState *env)
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{
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{
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return cpu_ppc_get_tb(env) & 0xFFFFFFFF;
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return cpu_ppc_get_tb(env);
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}
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}
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uint32_t cpu_ppc_load_tbu (CPUState *env)
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uint32_t cpu_ppc_load_tbu (CPUState *env)
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4
hw/ppc.c
4
hw/ppc.c
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@ -401,7 +401,7 @@ static inline uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk,
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return muldiv64(vmclk, tb_env->tb_freq, get_ticks_per_sec()) + tb_offset;
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return muldiv64(vmclk, tb_env->tb_freq, get_ticks_per_sec()) + tb_offset;
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}
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}
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uint32_t cpu_ppc_load_tbl (CPUState *env)
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uint64_t cpu_ppc_load_tbl (CPUState *env)
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{
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{
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ppc_tb_t *tb_env = env->tb_env;
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ppc_tb_t *tb_env = env->tb_env;
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uint64_t tb;
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uint64_t tb;
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@ -409,7 +409,7 @@ uint32_t cpu_ppc_load_tbl (CPUState *env)
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tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset);
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tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset);
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LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
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LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
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return tb & 0xFFFFFFFF;
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return tb;
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}
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}
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static inline uint32_t _cpu_ppc_load_tbu(CPUState *env)
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static inline uint32_t _cpu_ppc_load_tbu(CPUState *env)
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@ -1068,9 +1068,9 @@ static inline uint64_t cpu_ppc_get_tb (CPUState *env)
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return 0;
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return 0;
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}
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}
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uint32_t cpu_ppc_load_tbl (CPUState *env)
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uint64_t cpu_ppc_load_tbl (CPUState *env)
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{
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{
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return cpu_ppc_get_tb(env) & 0xFFFFFFFF;
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return cpu_ppc_get_tb(env);
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}
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}
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uint32_t cpu_ppc_load_tbu (CPUState *env)
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uint32_t cpu_ppc_load_tbu (CPUState *env)
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@ -741,7 +741,7 @@ int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def);
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/* Time-base and decrementer management */
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/* Time-base and decrementer management */
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#ifndef NO_CPU_IO_DEFS
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#ifndef NO_CPU_IO_DEFS
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uint32_t cpu_ppc_load_tbl (CPUPPCState *env);
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uint64_t cpu_ppc_load_tbl (CPUPPCState *env);
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uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
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uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
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void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
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void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
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void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
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void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
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@ -68,7 +68,7 @@ void helper_store_dump_spr (uint32_t sprn)
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target_ulong helper_load_tbl (void)
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target_ulong helper_load_tbl (void)
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{
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{
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return cpu_ppc_load_tbl(env);
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return (target_ulong)cpu_ppc_load_tbl(env);
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}
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}
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target_ulong helper_load_tbu (void)
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target_ulong helper_load_tbu (void)
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