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target/arm: Use gvec for NEON_3R_VADD_VSUB insns 

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181011205206.3552-10-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2018-10-24 07:50:19 +01:00 committed by Peter Maydell
parent eabcd6faa9
commit e4717ae02d
1 changed files with 10 additions and 19 deletions
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29
target/arm/translate.c
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@ -5949,6 +5949,16 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
break;
}
return 0;
case NEON_3R_VADD_VSUB:
if (u) {
tcg_gen_gvec_sub(size, rd_ofs, rn_ofs, rm_ofs,
vec_size, vec_size);
} else {
tcg_gen_gvec_add(size, rd_ofs, rn_ofs, rm_ofs,
vec_size, vec_size);
}
return 0;
}
if (size == 3) {
/* 64-bit element instructions. */
@ -6006,13 +6016,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
cpu_V1, cpu_V0);
}
break;
case NEON_3R_VADD_VSUB:
if (u) {
tcg_gen_sub_i64(CPU_V001);
} else {
tcg_gen_add_i64(CPU_V001);
}
break;
default:
abort();
}
@ -6147,18 +6150,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
tmp2 = neon_load_reg(rd, pass);
gen_neon_add(size, tmp, tmp2);
break;
case NEON_3R_VADD_VSUB:
if (!u) { /* VADD */
gen_neon_add(size, tmp, tmp2);
} else { /* VSUB */
switch (size) {
case 0: gen_helper_neon_sub_u8(tmp, tmp, tmp2); break;
case 1: gen_helper_neon_sub_u16(tmp, tmp, tmp2); break;
case 2: tcg_gen_sub_i32(tmp, tmp, tmp2); break;
default: abort();
}
}
break;
case NEON_3R_VTST_VCEQ:
if (!u) { /* VTST */
switch (size) {