mirror of https://gitee.com/openkylin/qemu.git
tcg: Make 32-bit multiword operations optional for 64-bit hosts
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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@ -114,6 +114,10 @@ typedef enum {
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#define TCG_TARGET_HAS_nor_i64 0
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#define TCG_TARGET_HAS_deposit_i64 1
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#define TCG_TARGET_HAS_movcond_i64 1
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#define TCG_TARGET_HAS_add2_i32 0
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#define TCG_TARGET_HAS_sub2_i32 0
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#define TCG_TARGET_HAS_mulu2_i32 0
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#endif
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#define TCG_TARGET_deposit_i32_valid(ofs, len) \
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@ -136,6 +136,9 @@ typedef enum {
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#define TCG_TARGET_HAS_movcond_i64 1
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#define TCG_TARGET_HAS_deposit_i32 1
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#define TCG_TARGET_HAS_deposit_i64 1
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#define TCG_TARGET_HAS_add2_i32 0
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#define TCG_TARGET_HAS_sub2_i32 0
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#define TCG_TARGET_HAS_mulu2_i32 0
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#define TCG_TARGET_deposit_i32_valid(ofs, len) ((len) <= 16)
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#define TCG_TARGET_deposit_i64_valid(ofs, len) ((len) <= 16)
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@ -85,6 +85,9 @@ typedef enum {
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#define TCG_TARGET_HAS_nor_i32 0
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#define TCG_TARGET_HAS_deposit_i32 0
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#define TCG_TARGET_HAS_movcond_i32 0
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#define TCG_TARGET_HAS_add2_i32 0
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#define TCG_TARGET_HAS_sub2_i32 0
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#define TCG_TARGET_HAS_mulu2_i32 0
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#define TCG_TARGET_HAS_div_i64 1
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#define TCG_TARGET_HAS_rot_i64 0
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@ -65,6 +65,9 @@ typedef enum TCGReg {
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#define TCG_TARGET_HAS_nor_i32 0
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#define TCG_TARGET_HAS_deposit_i32 0
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#define TCG_TARGET_HAS_movcond_i32 0
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#define TCG_TARGET_HAS_add2_i32 0
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#define TCG_TARGET_HAS_sub2_i32 0
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#define TCG_TARGET_HAS_mulu2_i32 0
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#if TCG_TARGET_REG_BITS == 64
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#define TCG_TARGET_HAS_div2_i64 1
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@ -124,6 +124,10 @@ typedef enum {
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#define TCG_TARGET_HAS_nor_i64 0
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#define TCG_TARGET_HAS_deposit_i64 0
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#define TCG_TARGET_HAS_movcond_i64 1
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#define TCG_TARGET_HAS_add2_i32 0
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#define TCG_TARGET_HAS_sub2_i32 0
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#define TCG_TARGET_HAS_mulu2_i32 0
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#endif
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#define TCG_AREG0 TCG_REG_I0
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@ -83,10 +83,10 @@ DEF(deposit_i32, 1, 2, 2, IMPL(TCG_TARGET_HAS_deposit_i32))
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DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END)
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DEF(add2_i32, 2, 4, 0, IMPL(TCG_TARGET_REG_BITS == 32))
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DEF(sub2_i32, 2, 4, 0, IMPL(TCG_TARGET_REG_BITS == 32))
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DEF(add2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_add2_i32))
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DEF(sub2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_sub2_i32))
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DEF(mulu2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_mulu2_i32))
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DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | IMPL(TCG_TARGET_REG_BITS == 32))
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DEF(mulu2_i32, 2, 2, 0, IMPL(TCG_TARGET_REG_BITS == 32))
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DEF(setcond2_i32, 1, 4, 1, IMPL(TCG_TARGET_REG_BITS == 32))
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DEF(ext8s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8s_i32))
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@ -57,8 +57,8 @@ typedef uint64_t TCGRegSet;
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#error unsupported
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#endif
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/* Turn some undef macros into false macros. */
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#if TCG_TARGET_REG_BITS == 32
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/* Turn some undef macros into false macros. */
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#define TCG_TARGET_HAS_div_i64 0
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#define TCG_TARGET_HAS_div2_i64 0
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#define TCG_TARGET_HAS_rot_i64 0
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@ -80,6 +80,10 @@ typedef uint64_t TCGRegSet;
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#define TCG_TARGET_HAS_nor_i64 0
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#define TCG_TARGET_HAS_deposit_i64 0
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#define TCG_TARGET_HAS_movcond_i64 0
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/* Turn some undef macros into true macros. */
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#define TCG_TARGET_HAS_add2_i32 1
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#define TCG_TARGET_HAS_sub2_i32 1
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#define TCG_TARGET_HAS_mulu2_i32 1
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#endif
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#ifndef TCG_TARGET_deposit_i32_valid
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@ -100,6 +100,10 @@
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#define TCG_TARGET_HAS_orc_i64 0
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#define TCG_TARGET_HAS_rot_i64 1
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#define TCG_TARGET_HAS_movcond_i64 0
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#define TCG_TARGET_HAS_add2_i32 0
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#define TCG_TARGET_HAS_sub2_i32 0
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#define TCG_TARGET_HAS_mulu2_i32 0
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#endif /* TCG_TARGET_REG_BITS == 64 */
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/* Number of registers available.
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