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target/arm: Convert T16, extract 

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190904193059.26202-57-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2019-09-04 12:30:46 -07:00 committed by Peter Maydell
parent 2e6a646d7b
commit e6f69612cc
2 changed files with 11 additions and 13 deletions
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10
target/arm/t16.decode
View File

@ -23,6 +23,7 @@
&s_rrr_shr !extern s rn rd rm rs shty &s_rrr_shr !extern s rn rd rm rs shty
&s_rri_rot !extern s rn rd imm rot &s_rri_rot !extern s rn rd imm rot
&s_rrrr !extern s rd rn rm ra &s_rrrr !extern s rd rn rm ra
&rrr_rot !extern rd rn rm rot
&ri !extern rd imm &ri !extern rd imm
&r !extern rm &r !extern rm
&ldst_rr !extern p w u rn rt rm shimm shtype &ldst_rr !extern p w u rn rt rm shimm shtype
@ -173,3 +174,12 @@ BX 0100 0111 0 .... 000 @branchr
BLX_r 0100 0111 1 .... 000 @branchr BLX_r 0100 0111 1 .... 000 @branchr
BXNS 0100 0111 0 .... 100 @branchr BXNS 0100 0111 0 .... 100 @branchr
BLXNS 0100 0111 1 .... 100 @branchr BLXNS 0100 0111 1 .... 100 @branchr
# Extend
@extend .... .... .. rm:3 rd:3 &rrr_rot rn=15 rot=0
SXTAH 1011 0010 00 ... ... @extend
SXTAB 1011 0010 01 ... ... @extend
UXTAH 1011 0010 10 ... ... @extend
UXTAB 1011 0010 11 ... ... @extend

14
target/arm/translate.c
View File

@ -10766,21 +10766,9 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
op = (insn >> 8) & 0xf; op = (insn >> 8) & 0xf;
switch (op) { switch (op) {
case 0: /* add/sub (sp, immediate), in decodetree */ case 0: /* add/sub (sp, immediate), in decodetree */
case 2: /* sign/zero extend, in decodetree */
goto illegal_op; goto illegal_op;
case 2: /* sign/zero extend. */
ARCH(6);
rd = insn & 7;
rm = (insn >> 3) & 7;
tmp = load_reg(s, rm);
switch ((insn >> 6) & 3) {
case 0: gen_sxth(tmp); break;
case 1: gen_sxtb(tmp); break;
case 2: gen_uxth(tmp); break;
case 3: gen_uxtb(tmp); break;
}
store_reg(s, rd, tmp);
break;
case 4: case 5: case 0xc: case 0xd: case 4: case 5: case 0xc: case 0xd:
/* /*
* 0b1011_x10x_xxxx_xxxx * 0b1011_x10x_xxxx_xxxx