mirror of https://gitee.com/openkylin/qemu.git
eepro100: Remove C++ comments
C++ comments are unwanted, so this is fixed here. * Replace C++ comments by C comments. * Put code which was deactivated by a C++ comment in #if 0...#endif. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Stefan Weil
Michael S. Tsirkin
parent
f80a7fc34e
commit
e7493b25c0
185
hw/eepro100.c
185
hw/eepro100.c
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@ -154,11 +154,13 @@ typedef struct {
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uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */
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uint8_t tx_threshold; /* transmit threshold */
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uint8_t tbd_count; /* TBD number */
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//~ /* This constitutes two "TBD" entries: hdr and data */
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//~ uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
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//~ int32_t tx_buf_size0; /* Length of Tx hdr. */
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//~ uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
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//~ int32_t tx_buf_size1; /* Length of Tx data. */
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#if 0
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/* This constitutes two "TBD" entries: hdr and data */
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uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
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int32_t tx_buf_size0; /* Length of Tx hdr. */
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uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
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int32_t tx_buf_size1; /* Length of Tx data. */
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#endif
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} eepro100_tx_t;
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/* Receive frame descriptor. */
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@ -398,7 +400,9 @@ static void eepro100_interrupt(EEPRO100State * s, uint8_t status)
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s->mem[SCBAck] |= status;
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status = s->scb_stat = s->mem[SCBAck];
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status &= (mask | 0x0f);
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//~ status &= (~s->mem[SCBIntmask] | 0x0xf);
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#if 0
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status &= (~s->mem[SCBIntmask] | 0x0xf);
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#endif
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if (status && (mask & 0x01)) {
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/* SCB mask and SCB Bit M do not disable interrupt. */
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enable_interrupt(s);
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@ -477,9 +481,11 @@ static void pci_reset(EEPRO100State * s)
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pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
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/* PCI Cache Line Size */
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/* check cache line size!!! */
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//~ PCI_CONFIG_8(0x0c, 0x00);
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#if 0
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PCI_CONFIG_8(0x0c, 0x00);
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#endif
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/* PCI Latency Timer */
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PCI_CONFIG_8(PCI_LATENCY_TIMER, 0x20); // latency timer = 32 clocks
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PCI_CONFIG_8(PCI_LATENCY_TIMER, 0x20); /* latency timer = 32 clocks */
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/* PCI Header Type */
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/* BIST (built-in self test) */
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/* Expansion ROM Base Address (depends on boot disable!!!) */
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@ -492,7 +498,7 @@ static void pci_reset(EEPRO100State * s)
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/* Interrupt Line */
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/* Interrupt Pin */
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/* TODO: RST# value should be 0 */
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PCI_CONFIG_8(PCI_INTERRUPT_PIN, 1); // interrupt pin 0
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PCI_CONFIG_8(PCI_INTERRUPT_PIN, 1); /* interrupt pin 0 */
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/* Minimum Grant */
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PCI_CONFIG_8(PCI_MIN_GNT, 0x08);
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/* Maximum Latency */
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@ -500,20 +506,20 @@ static void pci_reset(EEPRO100State * s)
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switch (device) {
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case i82550:
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// TODO: check device id.
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/* TODO: check device id. */
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pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
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/* Revision ID: 0x0c, 0x0d, 0x0e. */
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PCI_CONFIG_8(PCI_REVISION_ID, 0x0e);
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// TODO: check size of statistical counters.
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/* TODO: check size of statistical counters. */
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s->stats_size = 80;
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// TODO: check extended tcb support.
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/* TODO: check extended tcb support. */
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s->has_extended_tcb_support = 1;
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break;
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case i82551:
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pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
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/* Revision ID: 0x0f, 0x10. */
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PCI_CONFIG_8(PCI_REVISION_ID, 0x0f);
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// TODO: check size of statistical counters.
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/* TODO: check size of statistical counters. */
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s->stats_size = 80;
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s->has_extended_tcb_support = 1;
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break;
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@ -572,7 +578,7 @@ static void pci_reset(EEPRO100State * s)
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PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
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PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
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PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
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// TODO: Windows wants revision id 0x0c.
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/* TODO: Windows wants revision id 0x0c. */
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PCI_CONFIG_8(PCI_REVISION_ID, 0x0c);
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#if EEPROM_SIZE > 0
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PCI_CONFIG_16(PCI_SUBSYSTEM_VENDOR_ID, 0x8086);
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@ -590,7 +596,7 @@ static void pci_reset(EEPRO100State * s)
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s->has_extended_tcb_support = 1;
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break;
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case i82562:
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// TODO: check device id.
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/* TODO: check device id. */
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pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
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/* TODO: wrong revision id. */
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PCI_CONFIG_8(PCI_REVISION_ID, 0x0e);
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@ -637,14 +643,16 @@ static void pci_reset(EEPRO100State * s)
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#if EEPROM_SIZE > 0
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if (device == i82557C || device == i82558B || device == i82559C) {
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// TODO: get vendor id from EEPROM for i82557C or later.
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// TODO: get device id from EEPROM for i82557C or later.
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// TODO: status bit 4 can be disabled by EEPROM for i82558, i82559.
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// TODO: header type is determined by EEPROM for i82559.
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// TODO: get subsystem id from EEPROM for i82557C or later.
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// TODO: get subsystem vendor id from EEPROM for i82557C or later.
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// TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later.
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// TODO: capability pointer depends on EEPROM for i82558.
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/*
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TODO: get vendor id from EEPROM for i82557C or later.
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TODO: get device id from EEPROM for i82557C or later.
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TODO: status bit 4 can be disabled by EEPROM for i82558, i82559.
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TODO: header type is determined by EEPROM for i82559.
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TODO: get subsystem id from EEPROM for i82557C or later.
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TODO: get subsystem vendor id from EEPROM for i82557C or later.
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TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later.
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TODO: capability pointer depends on EEPROM for i82558.
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*/
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logout("Get device id and revision from EEPROM!!!\n");
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}
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#endif /* EEPROM_SIZE > 0 */
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@ -654,7 +662,9 @@ static void nic_selective_reset(EEPRO100State * s)
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{
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size_t i;
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uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom);
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//~ eeprom93xx_reset(s->eeprom);
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#if 0
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eeprom93xx_reset(s->eeprom);
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#endif
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memcpy(eeprom_contents, s->conf.macaddr.a, 6);
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eeprom_contents[EEPROM_ID] = EEPROM_ID_VALID;
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if (s->device == i82557B || s->device == i82557C)
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@ -738,7 +748,7 @@ static void eepro100_write_status(EEPRO100State * s, uint16_t val)
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static uint16_t eepro100_read_command(EEPRO100State * s)
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{
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uint16_t val = 0xffff;
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//~ TRACE(OTHER, logout("val=0x%04x\n", val));
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TRACE(OTHER, logout("val=0x%04x\n", val));
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return val;
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}
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#endif
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@ -793,9 +803,11 @@ static void dump_statistics(EEPRO100State * s)
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stl_le_phys(s->statsaddr + 36, s->statistics.rx_good_frames);
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stl_le_phys(s->statsaddr + 48, s->statistics.rx_resource_errors);
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stl_le_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors);
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//~ stw_le_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames);
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//~ stw_le_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames);
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//~ missing("CU dump statistical counters");
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#if 0
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stw_le_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames);
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stw_le_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames);
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missing("CU dump statistical counters");
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#endif
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}
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static void read_cb(EEPRO100State *s)
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@ -832,7 +844,9 @@ static void tx_command(EEPRO100State *s)
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while (size < tcb_bytes) {
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uint32_t tx_buffer_address = ldl_phys(tbd_address);
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uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
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//~ uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
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#if 0
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uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
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#endif
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tbd_address += 8;
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TRACE(RXTX, logout
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("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
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@ -889,7 +903,9 @@ static void tx_command(EEPRO100State *s)
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s->statistics.tx_good_frames++;
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/* Transmit with bad status would raise an CX/TNO interrupt.
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* (82557 only). Emulation never has bad status. */
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//~ eepro100_cx_interrupt(s);
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#if 0
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eepro100_cx_interrupt(s);
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#endif
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}
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static void set_multicast_list(EEPRO100State *s)
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@ -1016,7 +1032,9 @@ static void eepro100_cu_command(EEPRO100State * s, uint8_t val)
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logout("bad CU resume from CU state %u\n", get_cu_state(s));
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/* Workaround for bad Linux eepro100 driver which resumes
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* from idle state. */
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//~ missing("cu resume");
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#if 0
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missing("cu resume");
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#endif
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set_cu_state(s, cu_suspended);
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}
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if (get_cu_state(s) == cu_suspended) {
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@ -1067,7 +1085,9 @@ static void eepro100_ru_command(EEPRO100State * s, uint8_t val)
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/* RU start. */
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if (get_ru_state(s) != ru_idle) {
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logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle);
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//~ assert(!"wrong RU state");
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#if 0
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assert(!"wrong RU state");
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#endif
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}
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set_ru_state(s, ru_ready);
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s->ru_offset = s->pointer;
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@ -1078,7 +1098,9 @@ static void eepro100_ru_command(EEPRO100State * s, uint8_t val)
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if (get_ru_state(s) != ru_suspended) {
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logout("RU state is %u, should be %u\n", get_ru_state(s),
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ru_suspended);
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//~ assert(!"wrong RU state");
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#if 0
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assert(!"wrong RU state");
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#endif
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}
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set_ru_state(s, ru_ready);
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break;
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@ -1140,7 +1162,9 @@ static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val)
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TRACE(EEPROM, logout("val=0x%02x\n", val));
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/* mask unwriteable bits */
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//~ val = SET_MASKED(val, 0x31, eeprom->value);
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#if 0
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val = SET_MASKED(val, 0x31, eeprom->value);
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#endif
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int eecs = ((val & EEPROM_CS) != 0);
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int eesk = ((val & EEPROM_SK) != 0);
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@ -1222,7 +1246,9 @@ static void eepro100_write_mdi(EEPRO100State * s, uint32_t val)
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val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data));
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if (phy != 1) {
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/* Unsupported PHY address. */
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//~ logout("phy must be 1 but is %u\n", phy);
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#if 0
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logout("phy must be 1 but is %u\n", phy);
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#endif
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data = 0;
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} else if (opcode != 1 && opcode != 2) {
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/* Unsupported opcode. */
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@ -1368,16 +1394,22 @@ static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr)
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switch (addr) {
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case SCBStatus:
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//~ val = eepro100_read_status(s);
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#if 0
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val = eepro100_read_status(s);
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#endif
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TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
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break;
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case SCBAck:
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//~ val = eepro100_read_status(s);
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#if 0
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val = eepro100_read_status(s);
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#endif
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TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
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break;
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case SCBCmd:
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TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
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//~ val = eepro100_read_command(s);
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#if 0
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val = eepro100_read_command(s);
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#endif
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break;
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case SCBIntmask:
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TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
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@ -1413,7 +1445,9 @@ static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr)
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switch (addr) {
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case SCBStatus:
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//~ val = eepro100_read_status(s);
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#if 0
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val = eepro100_read_status(s);
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#endif
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case SCBCmd:
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TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
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break;
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@ -1437,11 +1471,15 @@ static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr)
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switch (addr) {
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case SCBStatus:
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//~ val = eepro100_read_status(s);
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#if 0
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val = eepro100_read_status(s);
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#endif
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TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
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break;
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case SCBPointer:
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//~ val = eepro100_read_pointer(s);
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#if 0
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val = eepro100_read_pointer(s);
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#endif
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TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
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break;
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case SCBPort:
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@ -1468,7 +1506,9 @@ static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val)
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switch (addr) {
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case SCBStatus:
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//~ eepro100_write_status(s, val);
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#if 0
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eepro100_write_status(s, val);
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#endif
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break;
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case SCBAck:
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eepro100_acknowledge(s);
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@ -1508,7 +1548,9 @@ static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val)
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switch (addr) {
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case SCBStatus:
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//~ eepro100_write_status(s, val);
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#if 0
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eepro100_write_status(s, val);
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#endif
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eepro100_acknowledge(s);
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break;
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case SCBCmd:
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@ -1556,7 +1598,9 @@ static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val)
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static uint32_t ioport_read1(void *opaque, uint32_t addr)
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{
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EEPRO100State *s = opaque;
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//~ logout("addr=%s\n", regname(addr));
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#if 0
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logout("addr=%s\n", regname(addr));
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#endif
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return eepro100_read1(s, addr - s->region[1]);
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}
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@ -1575,7 +1619,9 @@ static uint32_t ioport_read4(void *opaque, uint32_t addr)
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static void ioport_write1(void *opaque, uint32_t addr, uint32_t val)
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{
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EEPRO100State *s = opaque;
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//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
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#if 0
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logout("addr=%s val=0x%02x\n", regname(addr), val);
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#endif
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eepro100_write1(s, addr - s->region[1], val);
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}
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@ -1623,42 +1669,54 @@ static void pci_map(PCIDevice * pci_dev, int region_num,
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static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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EEPRO100State *s = opaque;
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//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
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#if 0
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logout("addr=%s val=0x%02x\n", regname(addr), val);
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#endif
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eepro100_write1(s, addr, val);
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}
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static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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EEPRO100State *s = opaque;
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//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
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#if 0
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logout("addr=%s val=0x%02x\n", regname(addr), val);
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#endif
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eepro100_write2(s, addr, val);
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}
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static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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EEPRO100State *s = opaque;
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//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
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#if 0
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logout("addr=%s val=0x%02x\n", regname(addr), val);
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#endif
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eepro100_write4(s, addr, val);
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}
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static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr)
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{
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EEPRO100State *s = opaque;
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//~ logout("addr=%s\n", regname(addr));
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#if 0
|
||||
logout("addr=%s\n", regname(addr));
|
||||
#endif
|
||||
return eepro100_read1(s, addr);
|
||||
}
|
||||
|
||||
static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr)
|
||||
{
|
||||
EEPRO100State *s = opaque;
|
||||
//~ logout("addr=%s\n", regname(addr));
|
||||
#if 0
|
||||
logout("addr=%s\n", regname(addr));
|
||||
#endif
|
||||
return eepro100_read2(s, addr);
|
||||
}
|
||||
|
||||
static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr)
|
||||
{
|
||||
EEPRO100State *s = opaque;
|
||||
//~ logout("addr=%s\n", regname(addr));
|
||||
#if 0
|
||||
logout("addr=%s\n", regname(addr));
|
||||
#endif
|
||||
return eepro100_read4(s, addr);
|
||||
}
|
||||
|
||||
|
|
@ -1695,7 +1753,9 @@ static int nic_can_receive(VLANClientState *nc)
|
|||
EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
|
||||
TRACE(RXTX, logout("%p\n", s));
|
||||
return get_ru_state(s) == ru_ready;
|
||||
//~ return !eepro100_buffer_full(s);
|
||||
#if 0
|
||||
return !eepro100_buffer_full(s);
|
||||
#endif
|
||||
}
|
||||
|
||||
static ssize_t nic_receive(VLANClientState *nc, const uint8_t * buf, size_t size)
|
||||
|
|
@ -1724,13 +1784,15 @@ static ssize_t nic_receive(VLANClientState *nc, const uint8_t * buf, size_t size
|
|||
* Short frame is discarded */
|
||||
logout("%p received short frame (%zu byte)\n", s, size);
|
||||
s->statistics.rx_short_frame_errors++;
|
||||
//~ return -1;
|
||||
#if 0
|
||||
return -1;
|
||||
#endif
|
||||
} else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & BIT(3))) {
|
||||
/* Long frame and configuration byte 18/3 (long receive ok) not set:
|
||||
* Long frames are discarded. */
|
||||
logout("%p received long frame (%zu byte), ignored\n", s, size);
|
||||
return -1;
|
||||
} else if (memcmp(buf, s->conf.macaddr.a, 6) == 0) { // !!!
|
||||
} else if (memcmp(buf, s->conf.macaddr.a, 6) == 0) { /* !!! */
|
||||
/* Frame matches individual address. */
|
||||
/* TODO: check configuration byte 15/4 (ignore U/L). */
|
||||
TRACE(RXTX, logout("%p received frame for me, len=%zu\n", s, size));
|
||||
|
|
@ -1774,11 +1836,12 @@ static ssize_t nic_receive(VLANClientState *nc, const uint8_t * buf, size_t size
|
|||
/* TODO: RNR interrupt only at first failed frame? */
|
||||
eepro100_rnr_interrupt(s);
|
||||
s->statistics.rx_resource_errors++;
|
||||
//~ assert(!"no resources");
|
||||
#if 0
|
||||
assert(!"no resources");
|
||||
#endif
|
||||
return -1;
|
||||
}
|
||||
//~ !!!
|
||||
//~ $3 = {status = 0x0, command = 0xc000, link = 0x2d220, rx_buf_addr = 0x207dc, count = 0x0, size = 0x5f8, packet = {0x0 <repeats 1518 times>}}
|
||||
/* !!! */
|
||||
eepro100_rx_t rx;
|
||||
cpu_physical_memory_read(s->ru_base + s->ru_offset, (uint8_t *) & rx,
|
||||
offsetof(eepro100_rx_t, packet));
|
||||
|
|
@ -1799,14 +1862,18 @@ static ssize_t nic_receive(VLANClientState *nc, const uint8_t * buf, size_t size
|
|||
rfd_status);
|
||||
stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size);
|
||||
/* Early receive interrupt not supported. */
|
||||
//~ eepro100_er_interrupt(s);
|
||||
#if 0
|
||||
eepro100_er_interrupt(s);
|
||||
#endif
|
||||
/* Receive CRC Transfer not supported. */
|
||||
if (s->configuration[18] & BIT(2)) {
|
||||
missing("Receive CRC Transfer");
|
||||
return -1;
|
||||
}
|
||||
/* TODO: check stripping enable bit. */
|
||||
//~ assert(!(s->configuration[17] & BIT(0)));
|
||||
#if 0
|
||||
assert(!(s->configuration[17] & BIT(0)));
|
||||
#endif
|
||||
cpu_physical_memory_write(s->ru_base + s->ru_offset +
|
||||
offsetof(eepro100_rx_t, packet), buf, size);
|
||||
s->statistics.rx_good_frames++;
|
||||
|
|
|
|||
Loading…
Reference in New Issue