mirror of https://gitee.com/openkylin/qemu.git
Merge branch 'target-arm.for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm
* 'target-arm.for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm: arm: add dummy A9-specific cp15 registers target-arm: Ignore attempts to set invalid modes in CPSR target-arm: Don't use cpu_single_env in bank_number()
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commit
e7f929028c
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@ -149,6 +149,10 @@ typedef struct CPUARMState {
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uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
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uint32_t c15_i_min; /* Minimum D-cache dirty line index. */
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uint32_t c15_threadid; /* TI debugger thread-ID. */
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uint32_t c15_config_base_address; /* SCU base address. */
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uint32_t c15_diagnostic; /* diagnostic register */
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uint32_t c15_power_diagnostic;
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uint32_t c15_power_control; /* power control */
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} cp15;
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struct {
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@ -448,7 +452,7 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
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#define cpu_signal_handler cpu_arm_signal_handler
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#define cpu_list arm_cpu_list
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#define CPU_SAVE_VERSION 4
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#define CPU_SAVE_VERSION 5
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/* MMU modes definitions */
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#define MMU_MODE0_SUFFIX _kernel
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@ -463,6 +463,26 @@ void cpu_arm_close(CPUARMState *env)
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g_free(env);
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}
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static int bad_mode_switch(CPUState *env, int mode)
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{
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/* Return true if it is not valid for us to switch to
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* this CPU mode (ie all the UNPREDICTABLE cases in
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* the ARM ARM CPSRWriteByInstr pseudocode).
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*/
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switch (mode) {
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case ARM_CPU_MODE_USR:
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case ARM_CPU_MODE_SYS:
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case ARM_CPU_MODE_SVC:
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case ARM_CPU_MODE_ABT:
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case ARM_CPU_MODE_UND:
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case ARM_CPU_MODE_IRQ:
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case ARM_CPU_MODE_FIQ:
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return 0;
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default:
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return 1;
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}
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}
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uint32_t cpsr_read(CPUARMState *env)
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{
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int ZF;
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@ -499,7 +519,15 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
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}
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if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
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switch_mode(env, val & CPSR_M);
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if (bad_mode_switch(env, val & CPSR_M)) {
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/* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
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* We choose to ignore the attempt and leave the CPSR M field
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* untouched.
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*/
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mask &= ~CPSR_M;
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} else {
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switch_mode(env, val & CPSR_M);
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}
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}
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mask &= ~CACHED_CPSR_BITS;
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env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
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@ -642,7 +670,7 @@ uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
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extern int semihosting_enabled;
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/* Map CPU modes onto saved register banks. */
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static inline int bank_number (int mode)
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static inline int bank_number(CPUState *env, int mode)
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{
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switch (mode) {
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case ARM_CPU_MODE_USR:
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@ -659,7 +687,7 @@ static inline int bank_number (int mode)
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case ARM_CPU_MODE_FIQ:
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return 5;
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}
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cpu_abort(cpu_single_env, "Bad mode %x\n", mode);
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cpu_abort(env, "Bad mode %x\n", mode);
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return -1;
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}
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@ -680,12 +708,12 @@ void switch_mode(CPUState *env, int mode)
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memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
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}
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i = bank_number(old_mode);
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i = bank_number(env, old_mode);
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env->banked_r13[i] = env->regs[13];
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env->banked_r14[i] = env->regs[14];
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env->banked_spsr[i] = env->spsr;
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i = bank_number(mode);
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i = bank_number(env, mode);
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env->regs[13] = env->banked_r13[i];
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env->regs[14] = env->banked_r14[i];
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env->spsr = env->banked_spsr[i];
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@ -1768,6 +1796,20 @@ void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
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goto bad_reg;
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}
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}
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if (ARM_CPUID(env) == ARM_CPUID_CORTEXA9) {
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switch (crm) {
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case 0:
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if ((op1 == 0) && (op2 == 0)) {
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env->cp15.c15_power_control = val;
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} else if ((op1 == 0) && (op2 == 1)) {
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env->cp15.c15_diagnostic = val;
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} else if ((op1 == 0) && (op2 == 2)) {
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env->cp15.c15_power_diagnostic = val;
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}
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default:
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break;
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}
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}
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break;
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}
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return;
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@ -2111,6 +2153,40 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
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* 0x200 << ($rn & 0xfff), when MMU is off. */
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goto bad_reg;
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}
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if (ARM_CPUID(env) == ARM_CPUID_CORTEXA9) {
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switch (crm) {
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case 0:
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if ((op1 == 4) && (op2 == 0)) {
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/* The config_base_address should hold the value of
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* the peripheral base. ARM should get this from a CPU
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* object property, but that support isn't available in
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* December 2011. Default to 0 for now and board models
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* that care can set it by a private hook */
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return env->cp15.c15_config_base_address;
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} else if ((op1 == 0) && (op2 == 0)) {
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/* power_control should be set to maximum latency. Again,
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default to 0 and set by private hook */
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return env->cp15.c15_power_control;
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} else if ((op1 == 0) && (op2 == 1)) {
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return env->cp15.c15_diagnostic;
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} else if ((op1 == 0) && (op2 == 2)) {
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return env->cp15.c15_power_diagnostic;
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}
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break;
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case 1: /* NEON Busy */
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return 0;
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case 5: /* tlb lockdown */
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case 6:
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case 7:
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if ((op1 == 5) && (op2 == 2)) {
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return 0;
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}
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break;
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default:
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break;
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}
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goto bad_reg;
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}
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return 0;
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}
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bad_reg:
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@ -2125,7 +2201,7 @@ void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
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if ((env->uncached_cpsr & CPSR_M) == mode) {
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env->regs[13] = val;
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} else {
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env->banked_r13[bank_number(mode)] = val;
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env->banked_r13[bank_number(env, mode)] = val;
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}
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}
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@ -2134,7 +2210,7 @@ uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
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if ((env->uncached_cpsr & CPSR_M) == mode) {
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return env->regs[13];
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} else {
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return env->banked_r13[bank_number(mode)];
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return env->banked_r13[bank_number(env, mode)];
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}
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}
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@ -56,6 +56,9 @@ void cpu_save(QEMUFile *f, void *opaque)
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qemu_put_be32(f, env->cp15.c13_tls2);
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qemu_put_be32(f, env->cp15.c13_tls3);
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qemu_put_be32(f, env->cp15.c15_cpar);
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qemu_put_be32(f, env->cp15.c15_power_control);
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qemu_put_be32(f, env->cp15.c15_diagnostic);
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qemu_put_be32(f, env->cp15.c15_power_diagnostic);
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qemu_put_be32(f, env->features);
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@ -170,6 +173,9 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
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env->cp15.c13_tls2 = qemu_get_be32(f);
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env->cp15.c13_tls3 = qemu_get_be32(f);
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env->cp15.c15_cpar = qemu_get_be32(f);
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env->cp15.c15_power_control = qemu_get_be32(f);
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env->cp15.c15_diagnostic = qemu_get_be32(f);
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env->cp15.c15_power_diagnostic = qemu_get_be32(f);
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env->features = qemu_get_be32(f);
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