openkylin
/
qemu
mirror of https://gitee.com/openkylin/qemu.git
9
0
Fork 0
Code Issues Projects Releases Wiki Activity

target/xtensa: implement GPIO32 

GPIO32 is not in the core ISA, but it was widely used in Diamond Cores.
This implementation doesn't do actual I/O and doesn't handle the case of
GPIO32 state being a part of coprocessor.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
Max Filippov 2017-02-17 16:21:36 -08:00
parent d1e9b0068a
commit e98727417a
2 changed files with 54 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
target/xtensa/cpu.h
View File

@ -108,6 +108,7 @@ enum {
};
enum {
EXPSTATE = 230,
THREADPTR = 231,
FCR = 232,
FSR = 233,

53
target/xtensa/translate.c
View File

@ -204,6 +204,7 @@ static const XtensaReg sregnames[256] = {
};
static const XtensaReg uregnames[256] = {
[EXPSTATE] = XTENSA_REG_BITS("EXPSTATE", XTENSA_OPTION_ALL),
[THREADPTR] = XTENSA_REG("THREADPTR", XTENSA_OPTION_THREAD_POINTER),
[FCR] = XTENSA_REG("FCR", XTENSA_OPTION_FP_COPROCESSOR),
[FSR] = XTENSA_REG("FSR", XTENSA_OPTION_FP_COPROCESSOR),
@ -1513,6 +1514,13 @@ static void translate_clamps(DisasContext *dc, const uint32_t arg[],
}
}
static void translate_clrb_expstate(DisasContext *dc, const uint32_t arg[],
const uint32_t par[])
{
/* TODO: GPIO32 may be a part of coprocessor */
tcg_gen_andi_i32(cpu_UR[EXPSTATE], cpu_UR[EXPSTATE], ~(1u << arg[0]));
}
/* par[0]: privileged, par[1]: check memory access */
static void translate_dcache(DisasContext *dc, const uint32_t arg[],
const uint32_t par[])
@ -2008,6 +2016,15 @@ static void translate_quou(DisasContext *dc, const uint32_t arg[],
}
}
static void translate_read_impwire(DisasContext *dc, const uint32_t arg[],
const uint32_t par[])
{
if (gen_window_check1(dc, arg[0])) {
/* TODO: GPIO32 may be a part of coprocessor */
tcg_gen_movi_i32(cpu_R[arg[0]], 0);
}
}
static void translate_rer(DisasContext *dc, const uint32_t arg[],
const uint32_t par[])
{
@ -2152,6 +2169,13 @@ static void translate_rur(DisasContext *dc, const uint32_t arg[],
}
}
static void translate_setb_expstate(DisasContext *dc, const uint32_t arg[],
const uint32_t par[])
{
/* TODO: GPIO32 may be a part of coprocessor */
tcg_gen_ori_i32(cpu_UR[EXPSTATE], cpu_UR[EXPSTATE], 1u << arg[0]);
}
static void translate_s32c1i(DisasContext *dc, const uint32_t arg[],
const uint32_t par[])
{
@ -2440,6 +2464,15 @@ static void translate_wer(DisasContext *dc, const uint32_t arg[],
}
}
static void translate_wrmsk_expstate(DisasContext *dc, const uint32_t arg[],
const uint32_t par[])
{
if (gen_window_check2(dc, arg[0], arg[1])) {
/* TODO: GPIO32 may be a part of coprocessor */
tcg_gen_and_i32(cpu_UR[EXPSTATE], cpu_R[arg[0]], cpu_R[arg[1]]);
}
}
static void translate_wsr(DisasContext *dc, const uint32_t arg[],
const uint32_t par[])
{
@ -2700,6 +2733,9 @@ static const XtensaOpcodeOps core_ops[] = {
}, {
.name = "clamps",
.translate = translate_clamps,
}, {
.name = "clrb_expstate",
.translate = translate_clrb_expstate,
}, {
.name = "depbits",
.translate = translate_depbits,
@ -3262,6 +3298,9 @@ static const XtensaOpcodeOps core_ops[] = {
.name = "rdtlb1",
.translate = translate_rtlb,
.par = (const uint32_t[]){true, 1},
}, {
.name = "read_impwire",
.translate = translate_read_impwire,
}, {
.name = "rems",
.translate = translate_quos,
@ -3629,6 +3668,10 @@ static const XtensaOpcodeOps core_ops[] = {
}, {
.name = "rsync",
.translate = translate_nop,
}, {
.name = "rur.expstate",
.translate = translate_rur,
.par = (const uint32_t[]){EXPSTATE},
}, {
.name = "rur.fcr",
.translate = translate_rur,
@ -3679,6 +3722,9 @@ static const XtensaOpcodeOps core_ops[] = {
.name = "saltu",
.translate = translate_salt,
.par = (const uint32_t[]){TCG_COND_LTU},
}, {
.name = "setb_expstate",
.translate = translate_setb_expstate,
}, {
.name = "sext",
.translate = translate_sext,
@ -3769,6 +3815,9 @@ static const XtensaOpcodeOps core_ops[] = {
.name = "witlb",
.translate = translate_wtlb,
.par = (const uint32_t[]){false},
}, {
.name = "wrmsk_expstate",
.translate = translate_wrmsk_expstate,
}, {
.name = "wsr.176",
.translate = translate_wsr,
@ -4077,6 +4126,10 @@ static const XtensaOpcodeOps core_ops[] = {
.name = "wsr.windowstart",
.translate = translate_wsr,
.par = (const uint32_t[]){WINDOW_START},
}, {
.name = "wur.expstate",
.translate = translate_wur,
.par = (const uint32_t[]){EXPSTATE},
}, {
.name = "wur.fcr",
.translate = translate_wur,