mirror of https://gitee.com/openkylin/qemu.git
adding direct block chaining support - simplified branch code gen
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@630 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
parent
28fbe299c3
commit
e98a6e40a9
193
target-ppc/op.c
193
target-ppc/op.c
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@ -473,121 +473,94 @@ PPC_OP(setcrfbit)
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}
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/* Branch */
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#if 0
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#define EIP regs->nip
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#define TB_DO_JUMP(name, tb, n, target) JUMP_TB(name, tb, n, target)
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#else
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#define TB_DO_JUMP(name, tb, n, target) regs->nip = target;
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#endif
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#define __PPC_OP_B(name, target) \
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PPC_OP(name) \
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{ \
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TB_DO_JUMP(glue(op_, name), T1, 0, (target)); \
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RETURN(); \
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}
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#define __PPC_OP_BL(name, target, link) \
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PPC_OP(name) \
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{ \
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regs->lr = (link); \
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TB_DO_JUMP(glue(op_, name), T1, 0, (target)); \
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RETURN(); \
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}
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#define PPC_OP_B(name, target, link) \
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__PPC_OP_B(name, target); \
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__PPC_OP_BL(glue(name, l), target, link)
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#define __PPC_OP_BC(name, cond, target) \
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PPC_OP(name) \
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{ \
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if (cond) { \
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TB_DO_JUMP(glue(op_, name), T1, 1, (target)); \
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} else { \
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TB_DO_JUMP(glue(op_, name), T1, 0, PARAM(1)); \
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} \
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RETURN(); \
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}
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#define __PPC_OP_BCL(name, cond, target) \
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PPC_OP(name) \
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{ \
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regs->lr = PARAM(1); \
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if (cond) { \
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TB_DO_JUMP(glue(op_, name), T1, 1, (target)); \
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} else { \
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TB_DO_JUMP(glue(op_, name), T1, 0, PARAM(1)); \
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} \
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RETURN(); \
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}
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#define __PPC_OP_BCLRL(name, cond, target) \
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PPC_OP(name) \
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{ \
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T2 = (target); \
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regs->lr = PARAM(1); \
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if (cond) { \
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TB_DO_JUMP(glue(op_, name), T1, 1, T2); \
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} else { \
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TB_DO_JUMP(glue(op_, name), T1, 0, PARAM(1)); \
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} \
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RETURN(); \
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}
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#define _PPC_OP_BC(name, namel, cond, target) \
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__PPC_OP_BC(name, cond, target); \
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__PPC_OP_BCL(namel, cond, target)
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/* Branch to target */
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#define PPC_OP_BC(name, cond) \
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_PPC_OP_BC(b_##name, bl_##name, cond, PARAM(2))
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PPC_OP_B(b, PARAM(1), PARAM(2));
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PPC_OP_BC(ctr, (regs->ctr != 0));
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PPC_OP_BC(ctr_true, (regs->ctr != 0 && (T0 & PARAM(3)) != 0));
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PPC_OP_BC(ctr_false, (regs->ctr != 0 && (T0 & PARAM(3)) == 0));
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PPC_OP_BC(ctrz, (regs->ctr == 0));
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PPC_OP_BC(ctrz_true, (regs->ctr == 0 && (T0 & PARAM(3)) != 0));
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PPC_OP_BC(ctrz_false, (regs->ctr == 0 && (T0 & PARAM(3)) == 0));
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PPC_OP_BC(true, ((T0 & PARAM(3)) != 0));
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PPC_OP_BC(false, ((T0 & PARAM(3)) == 0));
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/* Branch to CTR */
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#define PPC_OP_BCCTR(name, cond) \
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_PPC_OP_BC(bctr_##name, bctrl_##name, cond, regs->ctr & ~0x03)
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PPC_OP_B(bctr, regs->ctr & ~0x03, PARAM(1));
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PPC_OP_BCCTR(ctr, (regs->ctr != 0));
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PPC_OP_BCCTR(ctr_true, (regs->ctr != 0 && (T0 & PARAM(2)) != 0));
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PPC_OP_BCCTR(ctr_false, (regs->ctr != 0 && (T0 & PARAM(2)) == 0));
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PPC_OP_BCCTR(ctrz, (regs->ctr == 0));
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PPC_OP_BCCTR(ctrz_true, (regs->ctr == 0 && (T0 & PARAM(2)) != 0));
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PPC_OP_BCCTR(ctrz_false, (regs->ctr == 0 && (T0 & PARAM(2)) == 0));
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PPC_OP_BCCTR(true, ((T0 & PARAM(2)) != 0));
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PPC_OP_BCCTR(false, ((T0 & PARAM(2)) == 0));
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/* Branch to LR */
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#define PPC_OP_BCLR(name, cond) \
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__PPC_OP_BC(blr_##name, cond, regs->lr & ~0x03); \
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__PPC_OP_BCLRL(blrl_##name, cond, regs->lr & ~0x03)
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__PPC_OP_B(blr, regs->lr & ~0x03);
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PPC_OP(blrl)
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PPC_OP(setlr)
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{
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T0 = regs->lr & ~0x03;
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regs->lr = PARAM(1);
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TB_DO_JUMP(op_blrl, T1, 0, T0);
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regs->lr = PARAM1;
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}
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PPC_OP(b)
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{
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JUMP_TB(b1, PARAM1, 0, PARAM2);
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}
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PPC_OP(b_T1)
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{
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regs->nip = T1;
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}
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PPC_OP(btest)
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{
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if (T0) {
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JUMP_TB(btest, PARAM1, 0, PARAM2);
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} else {
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JUMP_TB(btest, PARAM1, 1, PARAM3);
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}
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RETURN();
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}
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PPC_OP_BCLR(ctr, (regs->ctr != 0));
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PPC_OP_BCLR(ctr_true, (regs->ctr != 0 && (T0 & PARAM(2)) != 0));
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PPC_OP_BCLR(ctr_false, (regs->ctr != 0 && (T0 & PARAM(2)) == 0));
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PPC_OP_BCLR(ctrz, (regs->ctr == 0));
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PPC_OP_BCLR(ctrz_true, (regs->ctr == 0 && (T0 & PARAM(2)) != 0));
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PPC_OP_BCLR(ctrz_false, (regs->ctr == 0 && (T0 & PARAM(2)) == 0));
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PPC_OP_BCLR(true, ((T0 & PARAM(2)) != 0));
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PPC_OP_BCLR(false, ((T0 & PARAM(2)) == 0));
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PPC_OP(btest_T1)
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{
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if (T0) {
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regs->nip = T1 & ~3;
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} else {
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regs->nip = PARAM1;
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}
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RETURN();
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}
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PPC_OP(movl_T1_ctr)
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{
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T1 = regs->ctr;
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}
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PPC_OP(movl_T1_lr)
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{
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T1 = regs->lr;
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}
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/* tests with result in T0 */
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PPC_OP(test_ctr)
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{
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T0 = (regs->ctr != 0);
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}
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PPC_OP(test_ctr_true)
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{
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T0 = (regs->ctr != 0 && (T0 & PARAM(1)) != 0);
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}
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PPC_OP(test_ctr_false)
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{
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T0 = (regs->ctr != 0 && (T0 & PARAM(1)) == 0);
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}
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PPC_OP(test_ctrz)
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{
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T0 = (regs->ctr == 0);
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}
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PPC_OP(test_ctrz_true)
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{
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T0 = (regs->ctr == 0 && (T0 & PARAM(1)) != 0);
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}
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PPC_OP(test_ctrz_false)
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{
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T0 = (regs->ctr == 0 && (T0 & PARAM(1)) == 0);
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}
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PPC_OP(test_true)
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{
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T0 = ((T0 & PARAM(1)) != 0);
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}
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PPC_OP(test_false)
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{
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T0 = ((T0 & PARAM(1)) == 0);
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}
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/* CTR maintenance */
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PPC_OP(dec_ctr)
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@ -1501,118 +1501,6 @@ GEN_HANDLER(stfiwx, 0x1F, 0x17, 0x1E, 0x00000001, PPC_FLOAT)
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}
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/*** Branch ***/
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#define GEN_BCOND(name, opc1, opc2, opc3, prologue, \
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bl_ctr, b_ctr, bl_ctrz, b_ctrz, b, bl, \
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bl_ctr_true, b_ctr_true, bl_ctrz_true, b_ctrz_true, bl_true, b_true, \
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bl_ctr_false, b_ctr_false, bl_ctrz_false, b_ctrz_false, bl_false, b_false) \
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GEN_HANDLER(name, opc1, opc2, opc3, 0x00000000, PPC_FLOW) \
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{ \
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__attribute__ ((unused)) uint32_t target; \
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uint32_t bo = BO(ctx->opcode); \
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uint32_t bi = BI(ctx->opcode); \
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uint32_t mask; \
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gen_op_update_tb(ctx->tb_offset); \
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gen_op_update_decr(ctx->decr_offset); \
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gen_op_process_exceptions((uint32_t)ctx->nip - 4); \
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prologue; \
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/* gen_op_set_T1((uint32_t)ctx->tb);*/ \
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if ((bo & 0x4) == 0) \
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gen_op_dec_ctr(); \
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if (bo & 0x10) { \
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/* No CR condition */ \
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switch (bo & 0x6) { \
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case 0: \
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if (LK(ctx->opcode)) { \
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bl_ctr; \
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} else { \
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b_ctr; \
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} \
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break; \
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case 2: \
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if (LK(ctx->opcode)) { \
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bl_ctrz; \
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} else { \
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b_ctrz; \
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} \
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break; \
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case 4: \
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case 6: \
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if (LK(ctx->opcode)) { \
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bl; \
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} else { \
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b; \
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} \
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break; \
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default: \
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printf("ERROR: %s: unhandled ba case (%d)\n", __func__, bo); \
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RET_INVAL(); \
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break; \
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} \
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} else { \
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mask = 1 << (3 - (bi & 0x03)); \
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gen_op_load_crf_T0(bi >> 2); \
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if (bo & 0x8) { \
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switch (bo & 0x6) { \
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case 0: \
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if (LK(ctx->opcode)) { \
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bl_ctr_true; \
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} else { \
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b_ctr_true; \
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} \
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break; \
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case 2: \
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if (LK(ctx->opcode)) { \
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bl_ctrz_true; \
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} else { \
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b_ctrz_true; \
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} \
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break; \
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case 4: \
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case 6: \
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if (LK(ctx->opcode)) { \
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bl_true; \
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} else { \
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b_true; \
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} \
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break; \
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default: \
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printf("ERROR: %s: unhandled b case (%d)\n", __func__, bo); \
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RET_INVAL(); \
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break; \
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} \
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} else { \
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switch (bo & 0x6) { \
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case 0: \
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if (LK(ctx->opcode)) { \
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bl_ctr_false; \
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} else { \
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b_ctr_false; \
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} \
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break; \
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case 2: \
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if (LK(ctx->opcode)) { \
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bl_ctrz_false; \
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} else { \
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b_ctrz_false; \
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} \
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break; \
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case 4: \
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case 6: \
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if (LK(ctx->opcode)) { \
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bl_false; \
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} else { \
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b_false; \
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} \
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break; \
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default: \
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printf("ERROR: %s: unhandled bn case (%d)\n", __func__, bo); \
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RET_INVAL(); \
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break; \
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} \
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} \
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} \
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ctx->exception = EXCP_BRANCH; \
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}
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/* b ba bl bla */
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GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
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@ -1626,85 +1514,127 @@ GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
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target = (uint32_t)ctx->nip + li - 4;
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else
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target = li;
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// gen_op_set_T1((uint32_t)ctx->tb);
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if (LK(ctx->opcode)) {
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gen_op_bl(target, (uint32_t)ctx->nip);
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} else {
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gen_op_b(target);
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gen_op_setlr((uint32_t)ctx->nip);
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}
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gen_op_b((long)ctx->tb, target);
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ctx->exception = EXCP_BRANCH;
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}
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/* bc bca bcl bcla */
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GEN_BCOND(bc, 0x10, 0xFF, 0xFF,
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do {
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uint32_t li = s_ext16(BD(ctx->opcode));
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if (AA(ctx->opcode) == 0) {
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target = (uint32_t)ctx->nip + li - 4;
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} else {
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target = li;
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}
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} while (0),
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gen_op_bl_ctr((uint32_t)ctx->nip, target),
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gen_op_b_ctr((uint32_t)ctx->nip, target),
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gen_op_bl_ctrz((uint32_t)ctx->nip, target),
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gen_op_b_ctrz((uint32_t)ctx->nip, target),
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gen_op_b(target),
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gen_op_bl(target, (uint32_t)ctx->nip),
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gen_op_bl_ctr_true((uint32_t)ctx->nip, target, mask),
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gen_op_b_ctr_true((uint32_t)ctx->nip, target, mask),
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gen_op_bl_ctrz_true((uint32_t)ctx->nip, target, mask),
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gen_op_b_ctrz_true((uint32_t)ctx->nip, target, mask),
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gen_op_bl_true((uint32_t)ctx->nip, target, mask),
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gen_op_b_true((uint32_t)ctx->nip, target, mask),
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gen_op_bl_ctr_false((uint32_t)ctx->nip, target, mask),
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gen_op_b_ctr_false((uint32_t)ctx->nip, target, mask),
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gen_op_bl_ctrz_false((uint32_t)ctx->nip, target, mask),
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gen_op_b_ctrz_false((uint32_t)ctx->nip, target, mask),
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gen_op_bl_false((uint32_t)ctx->nip, target, mask),
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gen_op_b_false((uint32_t)ctx->nip, target, mask));
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#define BCOND_IM 0
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#define BCOND_LR 1
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#define BCOND_CTR 2
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/* bcctr bcctrl */
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GEN_BCOND(bcctr, 0x13, 0x10, 0x10, do { } while (0),
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gen_op_bctrl_ctr((uint32_t)ctx->nip),
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gen_op_bctr_ctr((uint32_t)ctx->nip),
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gen_op_bctrl_ctrz((uint32_t)ctx->nip),
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gen_op_bctr_ctrz((uint32_t)ctx->nip),
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gen_op_bctr(),
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gen_op_bctrl((uint32_t)ctx->nip),
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gen_op_bctrl_ctr_true((uint32_t)ctx->nip, mask),
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gen_op_bctr_ctr_true((uint32_t)ctx->nip, mask),
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gen_op_bctrl_ctrz_true((uint32_t)ctx->nip, mask),
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gen_op_bctr_ctrz_true((uint32_t)ctx->nip, mask),
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gen_op_bctrl_true((uint32_t)ctx->nip, mask),
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gen_op_bctr_true((uint32_t)ctx->nip, mask),
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gen_op_bctrl_ctr_false((uint32_t)ctx->nip, mask),
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gen_op_bctr_ctr_false((uint32_t)ctx->nip, mask),
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gen_op_bctrl_ctrz_false((uint32_t)ctx->nip, mask),
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gen_op_bctr_ctrz_false((uint32_t)ctx->nip, mask),
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gen_op_bctrl_false((uint32_t)ctx->nip, mask),
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gen_op_bctr_false((uint32_t)ctx->nip, mask))
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static inline void gen_bcond(DisasContext *ctx, int type)
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{
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uint32_t target = 0;
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uint32_t bo = BO(ctx->opcode);
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uint32_t bi = BI(ctx->opcode);
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uint32_t mask;
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uint32_t li;
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/* bclr bclrl */
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GEN_BCOND(bclr, 0x13, 0x10, 0x00, do { } while (0),
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gen_op_blrl_ctr((uint32_t)ctx->nip),
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gen_op_blr_ctr((uint32_t)ctx->nip),
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gen_op_blrl_ctrz((uint32_t)ctx->nip),
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gen_op_blr_ctrz((uint32_t)ctx->nip),
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gen_op_blr(),
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gen_op_blrl((uint32_t)ctx->nip),
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gen_op_blrl_ctr_true((uint32_t)ctx->nip, mask),
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gen_op_blr_ctr_true((uint32_t)ctx->nip, mask),
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gen_op_blrl_ctrz_true((uint32_t)ctx->nip, mask),
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gen_op_blr_ctrz_true((uint32_t)ctx->nip, mask),
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gen_op_blrl_true((uint32_t)ctx->nip, mask),
|
||||
gen_op_blr_true((uint32_t)ctx->nip, mask),
|
||||
gen_op_blrl_ctr_false((uint32_t)ctx->nip, mask),
|
||||
gen_op_blr_ctr_false((uint32_t)ctx->nip, mask),
|
||||
gen_op_blrl_ctrz_false((uint32_t)ctx->nip, mask),
|
||||
gen_op_blr_ctrz_false((uint32_t)ctx->nip, mask),
|
||||
gen_op_blrl_false((uint32_t)ctx->nip, mask),
|
||||
gen_op_blr_false((uint32_t)ctx->nip, mask))
|
||||
gen_op_update_tb(ctx->tb_offset);
|
||||
gen_op_update_decr(ctx->decr_offset);
|
||||
gen_op_process_exceptions((uint32_t)ctx->nip - 4);
|
||||
|
||||
if ((bo & 0x4) == 0)
|
||||
gen_op_dec_ctr();
|
||||
switch(type) {
|
||||
case BCOND_IM:
|
||||
li = s_ext16(BD(ctx->opcode));
|
||||
if (AA(ctx->opcode) == 0) {
|
||||
target = (uint32_t)ctx->nip + li - 4;
|
||||
} else {
|
||||
target = li;
|
||||
}
|
||||
break;
|
||||
case BCOND_CTR:
|
||||
gen_op_movl_T1_ctr();
|
||||
break;
|
||||
default:
|
||||
case BCOND_LR:
|
||||
gen_op_movl_T1_lr();
|
||||
break;
|
||||
}
|
||||
if (LK(ctx->opcode)) {
|
||||
gen_op_setlr((uint32_t)ctx->nip);
|
||||
}
|
||||
if (bo & 0x10) {
|
||||
/* No CR condition */
|
||||
switch (bo & 0x6) {
|
||||
case 0:
|
||||
gen_op_test_ctr();
|
||||
break;
|
||||
case 2:
|
||||
gen_op_test_ctrz();
|
||||
break;
|
||||
default:
|
||||
case 4:
|
||||
case 6:
|
||||
if (type == BCOND_IM) {
|
||||
gen_op_b((long)ctx->tb, target);
|
||||
} else {
|
||||
gen_op_b_T1();
|
||||
break;
|
||||
}
|
||||
goto no_test;
|
||||
}
|
||||
} else {
|
||||
mask = 1 << (3 - (bi & 0x03));
|
||||
gen_op_load_crf_T0(bi >> 2);
|
||||
if (bo & 0x8) {
|
||||
switch (bo & 0x6) {
|
||||
case 0:
|
||||
gen_op_test_ctr_true(mask);
|
||||
break;
|
||||
case 2:
|
||||
gen_op_test_ctrz_true(mask);
|
||||
break;
|
||||
default:
|
||||
case 4:
|
||||
case 6:
|
||||
gen_op_test_true(mask);
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
switch (bo & 0x6) {
|
||||
case 0:
|
||||
gen_op_test_ctr_false(mask);
|
||||
break;
|
||||
case 2:
|
||||
gen_op_test_ctrz_false(mask);
|
||||
break;
|
||||
default:
|
||||
case 4:
|
||||
case 6:
|
||||
gen_op_test_false(mask);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
if (type == BCOND_IM) {
|
||||
gen_op_btest((long)ctx->tb, target, (uint32_t)ctx->nip);
|
||||
} else {
|
||||
gen_op_btest_T1((uint32_t)ctx->nip);
|
||||
}
|
||||
no_test:
|
||||
ctx->exception = EXCP_BRANCH;
|
||||
}
|
||||
|
||||
GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
|
||||
{
|
||||
gen_bcond(ctx, BCOND_IM);
|
||||
}
|
||||
|
||||
GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
|
||||
{
|
||||
gen_bcond(ctx, BCOND_CTR);
|
||||
}
|
||||
|
||||
GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
|
||||
{
|
||||
gen_bcond(ctx, BCOND_LR);
|
||||
}
|
||||
|
||||
/*** Condition register logical ***/
|
||||
#define GEN_CRLOGIC(op, opc) \
|
||||
|
|
@ -3148,7 +3078,7 @@ int gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
|
|||
if (gen_opc_ptr >= gen_opc_end ||
|
||||
((uint32_t)ctx.nip - pc_start) >= (TARGET_PAGE_SIZE - 32)) {
|
||||
if (ctx.exception == EXCP_NONE) {
|
||||
gen_op_b((uint32_t)ctx.nip);
|
||||
gen_op_b((long)ctx.tb, (uint32_t)ctx.nip);
|
||||
ctx.exception = EXCP_BRANCH;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue