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ppc/ppc405: Use an embedded PPCUIC model in SoC state 

Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[balaton: Simplify sysbus device casts for readability]
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <ac5f010f4eb3ade061c65bc39a049f231f75574a.1660746880.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
This commit is contained in:
Cédric Le Goater 2022-08-17 17:08:34 +02:00 committed by Daniel Henrique Barboza
parent cba58aa762
commit e9d20f3717
2 changed files with 16 additions and 15 deletions
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3
hw/ppc/ppc405.h
View File

@ -27,6 +27,7 @@
#include "qom/object.h" #include "qom/object.h"
#include "hw/ppc/ppc4xx.h" #include "hw/ppc/ppc4xx.h"
#include "hw/intc/ppc-uic.h"
#define PPC405EP_SDRAM_BASE 0x00000000 #define PPC405EP_SDRAM_BASE 0x00000000
#define PPC405EP_NVRAM_BASE 0xF0000000 #define PPC405EP_NVRAM_BASE 0xF0000000
@ -208,7 +209,7 @@ struct Ppc405SoCState {
hwaddr ram_size; hwaddr ram_size;
PowerPCCPU cpu; PowerPCCPU cpu;
DeviceState *uic; PPCUIC uic;
Ppc405CpcState cpc; Ppc405CpcState cpc;
Ppc405GptState gpt; Ppc405GptState gpt;
Ppc405OcmState ocm; Ppc405OcmState ocm;

28
hw/ppc/ppc405_uc.c
View File

@ -1083,6 +1083,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "cpu", &s->cpu, object_initialize_child(obj, "cpu", &s->cpu,
POWERPC_CPU_TYPE_NAME("405ep")); POWERPC_CPU_TYPE_NAME("405ep"));
object_initialize_child(obj, "uic", &s->uic, TYPE_PPC_UIC);
object_initialize_child(obj, "cpc", &s->cpc, TYPE_PPC405_CPC); object_initialize_child(obj, "cpc", &s->cpc, TYPE_PPC405_CPC);
object_property_add_alias(obj, "sys-clk", OBJECT(&s->cpc), "sys-clk"); object_property_add_alias(obj, "sys-clk", OBJECT(&s->cpc), "sys-clk");
@ -1150,17 +1152,15 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(sbd, 0, 0xef600600); sysbus_mmio_map(sbd, 0, 0xef600600);
/* Universal interrupt controller */ /* Universal interrupt controller */
s->uic = qdev_new(TYPE_PPC_UIC); object_property_set_link(OBJECT(&s->uic), "cpu", OBJECT(&s->cpu),
object_property_set_link(OBJECT(s->uic), "cpu", OBJECT(&s->cpu),
&error_fatal); &error_fatal);
if (!sysbus_realize(SYS_BUS_DEVICE(s->uic), errp)) { sbd = SYS_BUS_DEVICE(&s->uic);
if (!sysbus_realize(sbd, errp)) {
return; return;
} }
sysbus_connect_irq(sbd, PPCUIC_OUTPUT_INT,
sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_INT,
qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_INT)); qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_INT));
sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_CINT, sysbus_connect_irq(sbd, PPCUIC_OUTPUT_CINT,
qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_CINT)); qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_CINT));
/* SDRAM controller */ /* SDRAM controller */
@ -1171,7 +1171,7 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
"ppc405.sdram0", s->dram_mr, "ppc405.sdram0", s->dram_mr,
s->ram_bases[0], s->ram_sizes[0]); s->ram_bases[0], s->ram_sizes[0]);
ppc4xx_sdram_init(env, qdev_get_gpio_in(s->uic, 17), 1, ppc4xx_sdram_init(env, qdev_get_gpio_in(DEVICE(&s->uic), 17), 1,
s->ram_banks, s->ram_bases, s->ram_sizes, s->ram_banks, s->ram_bases, s->ram_sizes,
s->do_dram_init); s->do_dram_init);
@ -1186,12 +1186,12 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
} }
sbd = SYS_BUS_DEVICE(&s->dma); sbd = SYS_BUS_DEVICE(&s->dma);
for (i = 0; i < ARRAY_SIZE(s->dma.irqs); i++) { for (i = 0; i < ARRAY_SIZE(s->dma.irqs); i++) {
sysbus_connect_irq(sbd, i, qdev_get_gpio_in(s->uic, 5 + i)); sysbus_connect_irq(sbd, i, qdev_get_gpio_in(DEVICE(&s->uic), 5 + i));
} }
/* I2C controller */ /* I2C controller */
sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500,
qdev_get_gpio_in(s->uic, 2)); qdev_get_gpio_in(DEVICE(&s->uic), 2));
/* GPIO */ /* GPIO */
sbd = SYS_BUS_DEVICE(&s->gpio); sbd = SYS_BUS_DEVICE(&s->gpio);
@ -1203,13 +1203,13 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
/* Serial ports */ /* Serial ports */
if (serial_hd(0) != NULL) { if (serial_hd(0) != NULL) {
serial_mm_init(get_system_memory(), 0xef600300, 0, serial_mm_init(get_system_memory(), 0xef600300, 0,
qdev_get_gpio_in(s->uic, 0), qdev_get_gpio_in(DEVICE(&s->uic), 0),
PPC_SERIAL_MM_BAUDBASE, serial_hd(0), PPC_SERIAL_MM_BAUDBASE, serial_hd(0),
DEVICE_BIG_ENDIAN); DEVICE_BIG_ENDIAN);
} }
if (serial_hd(1) != NULL) { if (serial_hd(1) != NULL) {
serial_mm_init(get_system_memory(), 0xef600400, 0, serial_mm_init(get_system_memory(), 0xef600400, 0,
qdev_get_gpio_in(s->uic, 1), qdev_get_gpio_in(DEVICE(&s->uic), 1),
PPC_SERIAL_MM_BAUDBASE, serial_hd(1), PPC_SERIAL_MM_BAUDBASE, serial_hd(1),
DEVICE_BIG_ENDIAN); DEVICE_BIG_ENDIAN);
} }
@ -1226,7 +1226,7 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
} }
sysbus_mmio_map(sbd, 0, 0xef600000); sysbus_mmio_map(sbd, 0, 0xef600000);
for (i = 0; i < ARRAY_SIZE(s->gpt.irqs); i++) { for (i = 0; i < ARRAY_SIZE(s->gpt.irqs); i++) {
sysbus_connect_irq(sbd, i, qdev_get_gpio_in(s->uic, 19 + i)); sysbus_connect_irq(sbd, i, qdev_get_gpio_in(DEVICE(&s->uic), 19 + i));
} }
/* MAL */ /* MAL */
@ -1237,7 +1237,7 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
} }
sbd = SYS_BUS_DEVICE(&s->mal); sbd = SYS_BUS_DEVICE(&s->mal);
for (i = 0; i < ARRAY_SIZE(s->mal.irqs); i++) { for (i = 0; i < ARRAY_SIZE(s->mal.irqs); i++) {
sysbus_connect_irq(sbd, i, qdev_get_gpio_in(s->uic, 11 + i)); sysbus_connect_irq(sbd, i, qdev_get_gpio_in(DEVICE(&s->uic), 11 + i));
} }
/* Ethernet */ /* Ethernet */