mirror of https://gitee.com/openkylin/qemu.git
target/ppc: Move Vector Compare Not Equal or Zero to decodetree
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220225210936.1749575-11-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Matheus Ferst
Cédric Le Goater
parent
6a394290df
commit
eb936dc074
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@ -142,16 +142,13 @@ DEF_HELPER_3(vabsduw, void, avr, avr, avr)
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DEF_HELPER_3(vavgsb, void, avr, avr, avr)
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DEF_HELPER_3(vavgsh, void, avr, avr, avr)
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DEF_HELPER_3(vavgsw, void, avr, avr, avr)
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DEF_HELPER_4(vcmpnezb, void, env, avr, avr, avr)
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DEF_HELPER_4(vcmpnezh, void, env, avr, avr, avr)
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DEF_HELPER_4(vcmpnezw, void, env, avr, avr, avr)
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DEF_HELPER_4(vcmpeqfp, void, env, avr, avr, avr)
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DEF_HELPER_4(vcmpgefp, void, env, avr, avr, avr)
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DEF_HELPER_4(vcmpgtfp, void, env, avr, avr, avr)
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DEF_HELPER_4(vcmpbfp, void, env, avr, avr, avr)
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DEF_HELPER_4(vcmpnezb_dot, void, env, avr, avr, avr)
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DEF_HELPER_4(vcmpnezh_dot, void, env, avr, avr, avr)
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DEF_HELPER_4(vcmpnezw_dot, void, env, avr, avr, avr)
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DEF_HELPER_FLAGS_4(VCMPNEZB, TCG_CALL_NO_RWG, void, avr, avr, avr, i32)
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DEF_HELPER_FLAGS_4(VCMPNEZH, TCG_CALL_NO_RWG, void, avr, avr, avr, i32)
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DEF_HELPER_FLAGS_4(VCMPNEZW, TCG_CALL_NO_RWG, void, avr, avr, avr, i32)
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DEF_HELPER_4(vcmpeqfp_dot, void, env, avr, avr, avr)
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DEF_HELPER_4(vcmpgefp_dot, void, env, avr, avr, avr)
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DEF_HELPER_4(vcmpgtfp_dot, void, env, avr, avr, avr)
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@ -397,6 +397,10 @@ VCMPNEB 000100 ..... ..... ..... . 0000000111 @VC
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VCMPNEH 000100 ..... ..... ..... . 0001000111 @VC
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VCMPNEW 000100 ..... ..... ..... . 0010000111 @VC
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VCMPNEZB 000100 ..... ..... ..... . 0100000111 @VC
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VCMPNEZH 000100 ..... ..... ..... . 0101000111 @VC
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VCMPNEZW 000100 ..... ..... ..... . 0110000111 @VC
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## Vector Bit Manipulation Instruction
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VCFUGED 000100 ..... ..... ..... 10101001101 @VX
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@ -662,46 +662,18 @@ VCF(ux, uint32_to_float32, u32)
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VCF(sx, int32_to_float32, s32)
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#undef VCF
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#define VCMPNE_DO(suffix, element, etype, cmpzero, record) \
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void helper_vcmpne##suffix(CPUPPCState *env, ppc_avr_t *r, \
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ppc_avr_t *a, ppc_avr_t *b) \
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{ \
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etype ones = (etype)-1; \
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etype all = ones; \
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etype result, none = 0; \
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int i; \
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\
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for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
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if (cmpzero) { \
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result = ((a->element[i] == 0) \
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|| (b->element[i] == 0) \
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|| (a->element[i] != b->element[i]) ? \
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ones : 0x0); \
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} else { \
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result = (a->element[i] != b->element[i]) ? ones : 0x0; \
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} \
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r->element[i] = result; \
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all &= result; \
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none |= result; \
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} \
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if (record) { \
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env->crf[6] = ((all != 0) << 3) | ((none == 0) << 1); \
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} \
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#define VCMPNEZ(NAME, ELEM) \
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void helper_##NAME(ppc_vsr_t *t, ppc_vsr_t *a, ppc_vsr_t *b, uint32_t desc) \
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{ \
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for (int i = 0; i < ARRAY_SIZE(t->ELEM); i++) { \
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t->ELEM[i] = ((a->ELEM[i] == 0) || (b->ELEM[i] == 0) || \
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(a->ELEM[i] != b->ELEM[i])) ? -1 : 0; \
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} \
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}
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/*
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* VCMPNEZ - Vector compare not equal to zero
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* suffix - instruction mnemonic suffix (b: byte, h: halfword, w: word)
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* element - element type to access from vector
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*/
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#define VCMPNE(suffix, element, etype, cmpzero) \
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VCMPNE_DO(suffix, element, etype, cmpzero, 0) \
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VCMPNE_DO(suffix##_dot, element, etype, cmpzero, 1)
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VCMPNE(zb, u8, uint8_t, 1)
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VCMPNE(zh, u16, uint16_t, 1)
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VCMPNE(zw, u32, uint32_t, 1)
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#undef VCMPNE_DO
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#undef VCMPNE
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VCMPNEZ(VCMPNEZB, u8)
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VCMPNEZ(VCMPNEZH, u16)
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VCMPNEZ(VCMPNEZW, u32)
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#undef VCMPNEZ
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#define VCMPFP_DO(suffix, compare, order, record) \
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void helper_vcmp##suffix(CPUPPCState *env, ppc_avr_t *r, \
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@ -985,10 +985,6 @@ static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
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} \
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}
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GEN_VXRFORM(vcmpnezb, 3, 4)
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GEN_VXRFORM(vcmpnezh, 3, 5)
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GEN_VXRFORM(vcmpnezw, 3, 6)
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static void do_vcmp_rc(int vrt)
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{
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TCGv_i64 tmp, set, clr;
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@ -1049,6 +1045,68 @@ TRANS_FLAGS2(ISA300, VCMPNEB, do_vcmp, TCG_COND_NE, MO_8)
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TRANS_FLAGS2(ISA300, VCMPNEH, do_vcmp, TCG_COND_NE, MO_16)
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TRANS_FLAGS2(ISA300, VCMPNEW, do_vcmp, TCG_COND_NE, MO_32)
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static void gen_vcmpnez_vec(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
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{
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TCGv_vec t0, t1, zero;
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t0 = tcg_temp_new_vec_matching(t);
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t1 = tcg_temp_new_vec_matching(t);
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zero = tcg_constant_vec_matching(t, vece, 0);
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tcg_gen_cmp_vec(TCG_COND_EQ, vece, t0, a, zero);
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tcg_gen_cmp_vec(TCG_COND_EQ, vece, t1, b, zero);
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tcg_gen_cmp_vec(TCG_COND_NE, vece, t, a, b);
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tcg_gen_or_vec(vece, t, t, t0);
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tcg_gen_or_vec(vece, t, t, t1);
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tcg_temp_free_vec(t0);
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tcg_temp_free_vec(t1);
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}
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static bool do_vcmpnez(DisasContext *ctx, arg_VC *a, int vece)
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{
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static const TCGOpcode vecop_list[] = {
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INDEX_op_cmp_vec, 0
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};
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static const GVecGen3 ops[3] = {
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{
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.fniv = gen_vcmpnez_vec,
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.fno = gen_helper_VCMPNEZB,
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.opt_opc = vecop_list,
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.vece = MO_8
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},
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{
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.fniv = gen_vcmpnez_vec,
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.fno = gen_helper_VCMPNEZH,
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.opt_opc = vecop_list,
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.vece = MO_16
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},
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{
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.fniv = gen_vcmpnez_vec,
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.fno = gen_helper_VCMPNEZW,
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.opt_opc = vecop_list,
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.vece = MO_32
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}
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};
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REQUIRE_INSNS_FLAGS2(ctx, ISA300);
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REQUIRE_VECTOR(ctx);
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tcg_gen_gvec_3(avr_full_offset(a->vrt), avr_full_offset(a->vra),
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avr_full_offset(a->vrb), 16, 16, &ops[vece]);
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if (a->rc) {
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do_vcmp_rc(a->vrt);
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}
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return true;
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}
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TRANS(VCMPNEZB, do_vcmpnez, MO_8)
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TRANS(VCMPNEZH, do_vcmpnez, MO_16)
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TRANS(VCMPNEZW, do_vcmpnez, MO_32)
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GEN_VXRFORM(vcmpeqfp, 3, 3)
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GEN_VXRFORM(vcmpgefp, 3, 7)
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GEN_VXRFORM(vcmpgtfp, 3, 11)
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@ -184,9 +184,6 @@ GEN_HANDLER2_E(name, str, 0x4, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ISA300),
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GEN_VXRFORM1_300(name, name, #name, opc2, opc3) \
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GEN_VXRFORM1_300(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
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GEN_VXRFORM_300(vcmpnezb, 3, 4)
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GEN_VXRFORM_300(vcmpnezh, 3, 5)
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GEN_VXRFORM_300(vcmpnezw, 3, 6)
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GEN_VXRFORM(vcmpeqfp, 3, 3)
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GEN_VXRFORM(vcmpgefp, 3, 7)
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GEN_VXRFORM(vcmpgtfp, 3, 11)
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