mirror of https://gitee.com/openkylin/qemu.git
cpu: Move synchronize_from_tb() to tcg_ops
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> [claudio: wrapped target code in CONFIG_TCG, reworded comments] Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210204163931.7358-5-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -213,8 +213,8 @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit)
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TARGET_FMT_lx "] %s\n",
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TARGET_FMT_lx "] %s\n",
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last_tb->tc.ptr, last_tb->pc,
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last_tb->tc.ptr, last_tb->pc,
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lookup_symbol(last_tb->pc));
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lookup_symbol(last_tb->pc));
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if (cc->synchronize_from_tb) {
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if (cc->tcg_ops.synchronize_from_tb) {
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cc->synchronize_from_tb(cpu, last_tb);
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cc->tcg_ops.synchronize_from_tb(cpu, last_tb);
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} else {
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} else {
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assert(cc->set_pc);
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assert(cc->set_pc);
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cc->set_pc(cpu, last_tb->pc);
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cc->set_pc(cpu, last_tb->pc);
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@ -86,6 +86,19 @@ typedef struct TcgCpuOperations {
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* Called when the first CPU is realized.
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* Called when the first CPU is realized.
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*/
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*/
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void (*initialize)(void);
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void (*initialize)(void);
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/**
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* @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock
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*
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* This is called when we abandon execution of a TB before starting it,
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* and must set all parts of the CPU state which the previous TB in the
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* chain may not have updated.
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* By default, when this is NULL, a call is made to @set_pc(tb->pc).
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*
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* If more state needs to be restored, the target must implement a
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* function to restore all the state, and register it here.
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*/
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void (*synchronize_from_tb)(CPUState *cpu,
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const struct TranslationBlock *tb);
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} TcgCpuOperations;
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} TcgCpuOperations;
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@ -119,13 +132,6 @@ typedef struct TcgCpuOperations {
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* If the target behaviour here is anything other than "set
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* If the target behaviour here is anything other than "set
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* the PC register to the value passed in" then the target must
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* the PC register to the value passed in" then the target must
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* also implement the synchronize_from_tb hook.
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* also implement the synchronize_from_tb hook.
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* @synchronize_from_tb: Callback for synchronizing state from a TCG
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* #TranslationBlock. This is called when we abandon execution
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* of a TB before starting it, and must set all parts of the CPU
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* state which the previous TB in the chain may not have updated.
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* This always includes at least the program counter; some targets
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* will need to do more. If this hook is not implemented then the
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* default is to call @set_pc(tb->pc).
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* @tlb_fill: Callback for handling a softmmu tlb miss or user-only
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* @tlb_fill: Callback for handling a softmmu tlb miss or user-only
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* address fault. For system mode, if the access is valid, call
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* address fault. For system mode, if the access is valid, call
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* tlb_set_page and return true; if the access is invalid, and
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* tlb_set_page and return true; if the access is invalid, and
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@ -202,8 +208,6 @@ struct CPUClass {
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void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
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void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
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Error **errp);
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Error **errp);
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void (*set_pc)(CPUState *cpu, vaddr value);
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void (*set_pc)(CPUState *cpu, vaddr value);
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void (*synchronize_from_tb)(CPUState *cpu,
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const struct TranslationBlock *tb);
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bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
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bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr);
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bool probe, uintptr_t retaddr);
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@ -54,6 +54,7 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value)
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}
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}
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}
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}
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#ifdef CONFIG_TCG
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static void arm_cpu_synchronize_from_tb(CPUState *cs,
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static void arm_cpu_synchronize_from_tb(CPUState *cs,
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const TranslationBlock *tb)
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const TranslationBlock *tb)
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{
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{
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@ -70,6 +71,7 @@ static void arm_cpu_synchronize_from_tb(CPUState *cs,
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env->regs[15] = tb->pc;
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env->regs[15] = tb->pc;
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}
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}
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}
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}
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#endif /* CONFIG_TCG */
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static bool arm_cpu_has_work(CPUState *cs)
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static bool arm_cpu_has_work(CPUState *cs)
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{
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{
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@ -2257,7 +2259,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
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cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
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cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
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cc->dump_state = arm_cpu_dump_state;
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cc->dump_state = arm_cpu_dump_state;
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cc->set_pc = arm_cpu_set_pc;
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cc->set_pc = arm_cpu_set_pc;
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cc->synchronize_from_tb = arm_cpu_synchronize_from_tb;
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cc->gdb_read_register = arm_cpu_gdb_read_register;
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cc->gdb_read_register = arm_cpu_gdb_read_register;
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cc->gdb_write_register = arm_cpu_gdb_write_register;
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cc->gdb_write_register = arm_cpu_gdb_write_register;
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#ifndef CONFIG_USER_ONLY
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#ifndef CONFIG_USER_ONLY
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@ -2277,6 +2278,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
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cc->disas_set_info = arm_disas_set_info;
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cc->disas_set_info = arm_disas_set_info;
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#ifdef CONFIG_TCG
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#ifdef CONFIG_TCG
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cc->tcg_ops.initialize = arm_translate_init;
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cc->tcg_ops.initialize = arm_translate_init;
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cc->tcg_ops.synchronize_from_tb = arm_cpu_synchronize_from_tb;
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cc->tlb_fill = arm_cpu_tlb_fill;
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cc->tlb_fill = arm_cpu_tlb_fill;
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cc->debug_excp_handler = arm_debug_excp_handler;
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cc->debug_excp_handler = arm_debug_excp_handler;
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cc->debug_check_watchpoint = arm_debug_check_watchpoint;
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cc->debug_check_watchpoint = arm_debug_check_watchpoint;
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@ -208,7 +208,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
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cc->vmsd = &vms_avr_cpu;
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cc->vmsd = &vms_avr_cpu;
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cc->disas_set_info = avr_cpu_disas_set_info;
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cc->disas_set_info = avr_cpu_disas_set_info;
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cc->tcg_ops.initialize = avr_cpu_tcg_init;
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cc->tcg_ops.initialize = avr_cpu_tcg_init;
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cc->synchronize_from_tb = avr_cpu_synchronize_from_tb;
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cc->tcg_ops.synchronize_from_tb = avr_cpu_synchronize_from_tb;
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cc->gdb_read_register = avr_cpu_gdb_read_register;
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cc->gdb_read_register = avr_cpu_gdb_read_register;
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cc->gdb_write_register = avr_cpu_gdb_write_register;
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cc->gdb_write_register = avr_cpu_gdb_write_register;
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cc->gdb_num_core_regs = 35;
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cc->gdb_num_core_regs = 35;
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@ -144,7 +144,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
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cc->cpu_exec_interrupt = hppa_cpu_exec_interrupt;
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cc->cpu_exec_interrupt = hppa_cpu_exec_interrupt;
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cc->dump_state = hppa_cpu_dump_state;
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cc->dump_state = hppa_cpu_dump_state;
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cc->set_pc = hppa_cpu_set_pc;
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cc->set_pc = hppa_cpu_set_pc;
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cc->synchronize_from_tb = hppa_cpu_synchronize_from_tb;
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cc->tcg_ops.synchronize_from_tb = hppa_cpu_synchronize_from_tb;
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cc->gdb_read_register = hppa_cpu_gdb_read_register;
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cc->gdb_read_register = hppa_cpu_gdb_read_register;
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cc->gdb_write_register = hppa_cpu_gdb_write_register;
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cc->gdb_write_register = hppa_cpu_gdb_write_register;
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cc->tlb_fill = hppa_cpu_tlb_fill;
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cc->tlb_fill = hppa_cpu_tlb_fill;
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@ -61,7 +61,7 @@ void tcg_cpu_common_class_init(CPUClass *cc)
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{
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{
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cc->do_interrupt = x86_cpu_do_interrupt;
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cc->do_interrupt = x86_cpu_do_interrupt;
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cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
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cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
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cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
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cc->tcg_ops.synchronize_from_tb = x86_cpu_synchronize_from_tb;
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cc->cpu_exec_enter = x86_cpu_exec_enter;
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cc->cpu_exec_enter = x86_cpu_exec_enter;
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cc->cpu_exec_exit = x86_cpu_exec_exit;
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cc->cpu_exec_exit = x86_cpu_exec_exit;
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cc->tcg_ops.initialize = tcg_x86_init;
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cc->tcg_ops.initialize = tcg_x86_init;
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@ -369,7 +369,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
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cc->cpu_exec_interrupt = mb_cpu_exec_interrupt;
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cc->cpu_exec_interrupt = mb_cpu_exec_interrupt;
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cc->dump_state = mb_cpu_dump_state;
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cc->dump_state = mb_cpu_dump_state;
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cc->set_pc = mb_cpu_set_pc;
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cc->set_pc = mb_cpu_set_pc;
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cc->synchronize_from_tb = mb_cpu_synchronize_from_tb;
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cc->tcg_ops.synchronize_from_tb = mb_cpu_synchronize_from_tb;
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cc->gdb_read_register = mb_cpu_gdb_read_register;
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cc->gdb_read_register = mb_cpu_gdb_read_register;
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cc->gdb_write_register = mb_cpu_gdb_write_register;
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cc->gdb_write_register = mb_cpu_gdb_write_register;
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cc->tlb_fill = mb_cpu_tlb_fill;
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cc->tlb_fill = mb_cpu_tlb_fill;
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@ -257,6 +257,7 @@ static void mips_cpu_set_pc(CPUState *cs, vaddr value)
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}
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}
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}
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}
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#ifdef CONFIG_TCG
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static void mips_cpu_synchronize_from_tb(CPUState *cs,
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static void mips_cpu_synchronize_from_tb(CPUState *cs,
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const TranslationBlock *tb)
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const TranslationBlock *tb)
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{
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{
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@ -267,6 +268,7 @@ static void mips_cpu_synchronize_from_tb(CPUState *cs,
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env->hflags &= ~MIPS_HFLAG_BMASK;
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env->hflags &= ~MIPS_HFLAG_BMASK;
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env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
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env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
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}
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}
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#endif /* CONFIG_TCG */
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static bool mips_cpu_has_work(CPUState *cs)
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static bool mips_cpu_has_work(CPUState *cs)
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{
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{
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@ -678,7 +680,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
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cc->cpu_exec_interrupt = mips_cpu_exec_interrupt;
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cc->cpu_exec_interrupt = mips_cpu_exec_interrupt;
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cc->dump_state = mips_cpu_dump_state;
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cc->dump_state = mips_cpu_dump_state;
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cc->set_pc = mips_cpu_set_pc;
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cc->set_pc = mips_cpu_set_pc;
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cc->synchronize_from_tb = mips_cpu_synchronize_from_tb;
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cc->gdb_read_register = mips_cpu_gdb_read_register;
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cc->gdb_read_register = mips_cpu_gdb_read_register;
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cc->gdb_write_register = mips_cpu_gdb_write_register;
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cc->gdb_write_register = mips_cpu_gdb_write_register;
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#ifndef CONFIG_USER_ONLY
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#ifndef CONFIG_USER_ONLY
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@ -690,6 +691,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
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cc->disas_set_info = mips_cpu_disas_set_info;
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cc->disas_set_info = mips_cpu_disas_set_info;
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#ifdef CONFIG_TCG
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#ifdef CONFIG_TCG
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cc->tcg_ops.initialize = mips_tcg_init;
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cc->tcg_ops.initialize = mips_tcg_init;
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cc->tcg_ops.synchronize_from_tb = mips_cpu_synchronize_from_tb;
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cc->tlb_fill = mips_cpu_tlb_fill;
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cc->tlb_fill = mips_cpu_tlb_fill;
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#endif
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#endif
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@ -597,7 +597,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
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cc->cpu_exec_interrupt = riscv_cpu_exec_interrupt;
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cc->cpu_exec_interrupt = riscv_cpu_exec_interrupt;
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cc->dump_state = riscv_cpu_dump_state;
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cc->dump_state = riscv_cpu_dump_state;
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cc->set_pc = riscv_cpu_set_pc;
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cc->set_pc = riscv_cpu_set_pc;
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cc->synchronize_from_tb = riscv_cpu_synchronize_from_tb;
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cc->tcg_ops.synchronize_from_tb = riscv_cpu_synchronize_from_tb;
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cc->gdb_read_register = riscv_cpu_gdb_read_register;
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cc->gdb_read_register = riscv_cpu_gdb_read_register;
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cc->gdb_write_register = riscv_cpu_gdb_write_register;
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cc->gdb_write_register = riscv_cpu_gdb_write_register;
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cc->gdb_num_core_regs = 33;
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cc->gdb_num_core_regs = 33;
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@ -190,7 +190,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
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cc->cpu_exec_interrupt = rx_cpu_exec_interrupt;
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cc->cpu_exec_interrupt = rx_cpu_exec_interrupt;
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cc->dump_state = rx_cpu_dump_state;
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cc->dump_state = rx_cpu_dump_state;
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cc->set_pc = rx_cpu_set_pc;
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cc->set_pc = rx_cpu_set_pc;
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cc->synchronize_from_tb = rx_cpu_synchronize_from_tb;
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cc->tcg_ops.synchronize_from_tb = rx_cpu_synchronize_from_tb;
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cc->gdb_read_register = rx_cpu_gdb_read_register;
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cc->gdb_read_register = rx_cpu_gdb_read_register;
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cc->gdb_write_register = rx_cpu_gdb_write_register;
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cc->gdb_write_register = rx_cpu_gdb_write_register;
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cc->get_phys_page_debug = rx_cpu_get_phys_page_debug;
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cc->get_phys_page_debug = rx_cpu_get_phys_page_debug;
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@ -223,7 +223,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
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cc->cpu_exec_interrupt = superh_cpu_exec_interrupt;
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cc->cpu_exec_interrupt = superh_cpu_exec_interrupt;
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cc->dump_state = superh_cpu_dump_state;
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cc->dump_state = superh_cpu_dump_state;
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cc->set_pc = superh_cpu_set_pc;
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cc->set_pc = superh_cpu_set_pc;
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cc->synchronize_from_tb = superh_cpu_synchronize_from_tb;
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cc->tcg_ops.synchronize_from_tb = superh_cpu_synchronize_from_tb;
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cc->gdb_read_register = superh_cpu_gdb_read_register;
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cc->gdb_read_register = superh_cpu_gdb_read_register;
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cc->gdb_write_register = superh_cpu_gdb_write_register;
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cc->gdb_write_register = superh_cpu_gdb_write_register;
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cc->tlb_fill = superh_cpu_tlb_fill;
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cc->tlb_fill = superh_cpu_tlb_fill;
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@ -870,7 +870,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
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cc->memory_rw_debug = sparc_cpu_memory_rw_debug;
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cc->memory_rw_debug = sparc_cpu_memory_rw_debug;
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#endif
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#endif
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cc->set_pc = sparc_cpu_set_pc;
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cc->set_pc = sparc_cpu_set_pc;
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cc->synchronize_from_tb = sparc_cpu_synchronize_from_tb;
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cc->tcg_ops.synchronize_from_tb = sparc_cpu_synchronize_from_tb;
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cc->gdb_read_register = sparc_cpu_gdb_read_register;
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cc->gdb_read_register = sparc_cpu_gdb_read_register;
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cc->gdb_write_register = sparc_cpu_gdb_write_register;
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cc->gdb_write_register = sparc_cpu_gdb_write_register;
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cc->tlb_fill = sparc_cpu_tlb_fill;
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cc->tlb_fill = sparc_cpu_tlb_fill;
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@ -162,7 +162,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data)
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cc->dump_state = tricore_cpu_dump_state;
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cc->dump_state = tricore_cpu_dump_state;
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cc->set_pc = tricore_cpu_set_pc;
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cc->set_pc = tricore_cpu_set_pc;
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cc->synchronize_from_tb = tricore_cpu_synchronize_from_tb;
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cc->tcg_ops.synchronize_from_tb = tricore_cpu_synchronize_from_tb;
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cc->get_phys_page_debug = tricore_cpu_get_phys_page_debug;
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cc->get_phys_page_debug = tricore_cpu_get_phys_page_debug;
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cc->tcg_ops.initialize = tricore_tcg_init;
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cc->tcg_ops.initialize = tricore_tcg_init;
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cc->tlb_fill = tricore_cpu_tlb_fill;
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cc->tlb_fill = tricore_cpu_tlb_fill;
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