From ecd5f2882fdd10f798984eb52abd00ffc78c2ef7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Volker=20R=C3=BCmelin?= Date: Sun, 26 Dec 2021 16:40:17 +0100 Subject: [PATCH] hw/audio/intel-hda: fix stream reset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Quote from: High Definition Audio Specification 1.0a, section 3.3.35 Offset 80: {IOB}SDnCTL Stream Reset (SRST): Writing a 1 causes the corresponding stream to be reset. The Stream Descriptor registers (except the SRST bit itself) ... are reset. Change the code to reset the Stream Descriptor Control and Status registers except the SRST bit. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/757 Signed-off-by: Volker Rümelin Message-Id: <20211226154017.6067-3-vr_qemu@t-online.de> Signed-off-by: Gerd Hoffmann --- hw/audio/intel-hda.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/audio/intel-hda.c b/hw/audio/intel-hda.c index 2b55d52150..5f8a878f20 100644 --- a/hw/audio/intel-hda.c +++ b/hw/audio/intel-hda.c @@ -581,7 +581,7 @@ static void intel_hda_set_st_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint3 if (st->ctl & 0x01) { /* reset */ dprint(d, 1, "st #%d: reset\n", reg->stream); - st->ctl = SD_STS_FIFO_READY << 24; + st->ctl = SD_STS_FIFO_READY << 24 | SD_CTL_STREAM_RESET; } if ((st->ctl & 0x02) != (old & 0x02)) { uint32_t stnr = (st->ctl >> 20) & 0x0f;