mirror of https://gitee.com/openkylin/qemu.git
target/riscv: vector widening floating-point add/subtract instructions
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200701152549.1218-32-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
LIU Zhiwei
Alistair Francis
parent
ce2a0343f4
commit
eeffab2ec1
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@ -819,3 +819,20 @@ DEF_HELPER_6(vfsub_vf_d, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vfrsub_vf_h, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vfrsub_vf_w, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vfrsub_vf_d, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vfwadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vfwadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vfwsub_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vfwsub_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vfwadd_wv_h, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vfwadd_wv_w, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vfwsub_wv_h, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vfwsub_wv_w, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vfwadd_vf_h, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vfwadd_vf_w, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vfwsub_vf_h, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vfwsub_vf_w, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vfwadd_wf_h, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vfwadd_wf_w, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vfwsub_wf_h, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vfwsub_wf_w, void, ptr, ptr, i64, ptr, env, i32)
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@ -450,6 +450,14 @@ vfadd_vf 000000 . ..... ..... 101 ..... 1010111 @r_vm
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vfsub_vv 000010 . ..... ..... 001 ..... 1010111 @r_vm
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vfsub_vf 000010 . ..... ..... 101 ..... 1010111 @r_vm
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vfrsub_vf 100111 . ..... ..... 101 ..... 1010111 @r_vm
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vfwadd_vv 110000 . ..... ..... 001 ..... 1010111 @r_vm
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vfwadd_vf 110000 . ..... ..... 101 ..... 1010111 @r_vm
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vfwadd_wv 110100 . ..... ..... 001 ..... 1010111 @r_vm
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vfwadd_wf 110100 . ..... ..... 101 ..... 1010111 @r_vm
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vfwsub_vv 110010 . ..... ..... 001 ..... 1010111 @r_vm
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vfwsub_vf 110010 . ..... ..... 101 ..... 1010111 @r_vm
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vfwsub_wv 110110 . ..... ..... 001 ..... 1010111 @r_vm
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vfwsub_wf 110110 . ..... ..... 101 ..... 1010111 @r_vm
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vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
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vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
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@ -1901,3 +1901,152 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
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GEN_OPFVF_TRANS(vfadd_vf, opfvf_check)
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GEN_OPFVF_TRANS(vfsub_vf, opfvf_check)
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GEN_OPFVF_TRANS(vfrsub_vf, opfvf_check)
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/* Vector Widening Floating-Point Add/Subtract Instructions */
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static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
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{
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return (vext_check_isa_ill(s) &&
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vext_check_overlap_mask(s, a->rd, a->vm, true) &&
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vext_check_reg(s, a->rd, true) &&
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vext_check_reg(s, a->rs2, false) &&
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vext_check_reg(s, a->rs1, false) &&
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vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2,
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1 << s->lmul) &&
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vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1,
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1 << s->lmul) &&
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(s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
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}
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/* OPFVV with WIDEN */
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#define GEN_OPFVV_WIDEN_TRANS(NAME, CHECK) \
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static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
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{ \
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if (CHECK(s, a)) { \
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uint32_t data = 0; \
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static gen_helper_gvec_4_ptr * const fns[2] = { \
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gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
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}; \
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TCGLabel *over = gen_new_label(); \
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gen_set_rm(s, 7); \
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tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
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\
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data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
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data = FIELD_DP32(data, VDATA, VM, a->vm); \
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data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
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tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
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vreg_ofs(s, a->rs1), \
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vreg_ofs(s, a->rs2), cpu_env, 0, \
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s->vlen / 8, data, fns[s->sew - 1]); \
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gen_set_label(over); \
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return true; \
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} \
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return false; \
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}
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GEN_OPFVV_WIDEN_TRANS(vfwadd_vv, opfvv_widen_check)
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GEN_OPFVV_WIDEN_TRANS(vfwsub_vv, opfvv_widen_check)
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static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
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{
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return (vext_check_isa_ill(s) &&
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vext_check_overlap_mask(s, a->rd, a->vm, true) &&
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vext_check_reg(s, a->rd, true) &&
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vext_check_reg(s, a->rs2, false) &&
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vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2,
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1 << s->lmul) &&
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(s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
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}
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/* OPFVF with WIDEN */
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#define GEN_OPFVF_WIDEN_TRANS(NAME) \
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static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
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{ \
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if (opfvf_widen_check(s, a)) { \
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uint32_t data = 0; \
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static gen_helper_opfvf *const fns[2] = { \
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gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
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}; \
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gen_set_rm(s, 7); \
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data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
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data = FIELD_DP32(data, VDATA, VM, a->vm); \
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data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
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return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
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fns[s->sew - 1], s); \
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} \
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return false; \
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}
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GEN_OPFVF_WIDEN_TRANS(vfwadd_vf)
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GEN_OPFVF_WIDEN_TRANS(vfwsub_vf)
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static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
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{
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return (vext_check_isa_ill(s) &&
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vext_check_overlap_mask(s, a->rd, a->vm, true) &&
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vext_check_reg(s, a->rd, true) &&
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vext_check_reg(s, a->rs2, true) &&
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vext_check_reg(s, a->rs1, false) &&
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vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1,
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1 << s->lmul) &&
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(s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
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}
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/* WIDEN OPFVV with WIDEN */
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#define GEN_OPFWV_WIDEN_TRANS(NAME) \
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static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
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{ \
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if (opfwv_widen_check(s, a)) { \
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uint32_t data = 0; \
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static gen_helper_gvec_4_ptr * const fns[2] = { \
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gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
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}; \
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TCGLabel *over = gen_new_label(); \
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gen_set_rm(s, 7); \
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tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
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\
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data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
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data = FIELD_DP32(data, VDATA, VM, a->vm); \
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data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
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tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
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vreg_ofs(s, a->rs1), \
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vreg_ofs(s, a->rs2), cpu_env, 0, \
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s->vlen / 8, data, fns[s->sew - 1]); \
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gen_set_label(over); \
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return true; \
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} \
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return false; \
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}
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GEN_OPFWV_WIDEN_TRANS(vfwadd_wv)
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GEN_OPFWV_WIDEN_TRANS(vfwsub_wv)
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static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
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{
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return (vext_check_isa_ill(s) &&
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vext_check_overlap_mask(s, a->rd, a->vm, true) &&
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vext_check_reg(s, a->rd, true) &&
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vext_check_reg(s, a->rs2, true) &&
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(s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
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}
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/* WIDEN OPFVF with WIDEN */
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#define GEN_OPFWF_WIDEN_TRANS(NAME) \
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static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
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{ \
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if (opfwf_widen_check(s, a)) { \
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uint32_t data = 0; \
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static gen_helper_opfvf *const fns[2] = { \
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gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
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}; \
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gen_set_rm(s, 7); \
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data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
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data = FIELD_DP32(data, VDATA, VM, a->vm); \
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data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
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return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
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fns[s->sew - 1], s); \
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} \
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return false; \
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}
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GEN_OPFWF_WIDEN_TRANS(vfwadd_wf)
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GEN_OPFWF_WIDEN_TRANS(vfwsub_wf)
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@ -3278,3 +3278,86 @@ RVVCALL(OPFVF2, vfrsub_vf_d, OP_UUU_D, H8, H8, float64_rsub)
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GEN_VEXT_VF(vfrsub_vf_h, 2, 2, clearh)
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GEN_VEXT_VF(vfrsub_vf_w, 4, 4, clearl)
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GEN_VEXT_VF(vfrsub_vf_d, 8, 8, clearq)
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/* Vector Widening Floating-Point Add/Subtract Instructions */
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static uint32_t vfwadd16(uint16_t a, uint16_t b, float_status *s)
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{
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return float32_add(float16_to_float32(a, true, s),
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float16_to_float32(b, true, s), s);
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}
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static uint64_t vfwadd32(uint32_t a, uint32_t b, float_status *s)
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{
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return float64_add(float32_to_float64(a, s),
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float32_to_float64(b, s), s);
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}
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RVVCALL(OPFVV2, vfwadd_vv_h, WOP_UUU_H, H4, H2, H2, vfwadd16)
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RVVCALL(OPFVV2, vfwadd_vv_w, WOP_UUU_W, H8, H4, H4, vfwadd32)
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GEN_VEXT_VV_ENV(vfwadd_vv_h, 2, 4, clearl)
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GEN_VEXT_VV_ENV(vfwadd_vv_w, 4, 8, clearq)
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RVVCALL(OPFVF2, vfwadd_vf_h, WOP_UUU_H, H4, H2, vfwadd16)
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RVVCALL(OPFVF2, vfwadd_vf_w, WOP_UUU_W, H8, H4, vfwadd32)
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GEN_VEXT_VF(vfwadd_vf_h, 2, 4, clearl)
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GEN_VEXT_VF(vfwadd_vf_w, 4, 8, clearq)
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static uint32_t vfwsub16(uint16_t a, uint16_t b, float_status *s)
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{
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return float32_sub(float16_to_float32(a, true, s),
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float16_to_float32(b, true, s), s);
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}
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static uint64_t vfwsub32(uint32_t a, uint32_t b, float_status *s)
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{
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return float64_sub(float32_to_float64(a, s),
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float32_to_float64(b, s), s);
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}
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RVVCALL(OPFVV2, vfwsub_vv_h, WOP_UUU_H, H4, H2, H2, vfwsub16)
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RVVCALL(OPFVV2, vfwsub_vv_w, WOP_UUU_W, H8, H4, H4, vfwsub32)
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GEN_VEXT_VV_ENV(vfwsub_vv_h, 2, 4, clearl)
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GEN_VEXT_VV_ENV(vfwsub_vv_w, 4, 8, clearq)
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RVVCALL(OPFVF2, vfwsub_vf_h, WOP_UUU_H, H4, H2, vfwsub16)
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RVVCALL(OPFVF2, vfwsub_vf_w, WOP_UUU_W, H8, H4, vfwsub32)
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GEN_VEXT_VF(vfwsub_vf_h, 2, 4, clearl)
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GEN_VEXT_VF(vfwsub_vf_w, 4, 8, clearq)
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static uint32_t vfwaddw16(uint32_t a, uint16_t b, float_status *s)
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{
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return float32_add(a, float16_to_float32(b, true, s), s);
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}
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static uint64_t vfwaddw32(uint64_t a, uint32_t b, float_status *s)
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{
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return float64_add(a, float32_to_float64(b, s), s);
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}
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RVVCALL(OPFVV2, vfwadd_wv_h, WOP_WUUU_H, H4, H2, H2, vfwaddw16)
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RVVCALL(OPFVV2, vfwadd_wv_w, WOP_WUUU_W, H8, H4, H4, vfwaddw32)
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GEN_VEXT_VV_ENV(vfwadd_wv_h, 2, 4, clearl)
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GEN_VEXT_VV_ENV(vfwadd_wv_w, 4, 8, clearq)
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RVVCALL(OPFVF2, vfwadd_wf_h, WOP_WUUU_H, H4, H2, vfwaddw16)
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RVVCALL(OPFVF2, vfwadd_wf_w, WOP_WUUU_W, H8, H4, vfwaddw32)
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GEN_VEXT_VF(vfwadd_wf_h, 2, 4, clearl)
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GEN_VEXT_VF(vfwadd_wf_w, 4, 8, clearq)
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static uint32_t vfwsubw16(uint32_t a, uint16_t b, float_status *s)
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{
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return float32_sub(a, float16_to_float32(b, true, s), s);
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}
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static uint64_t vfwsubw32(uint64_t a, uint32_t b, float_status *s)
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{
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return float64_sub(a, float32_to_float64(b, s), s);
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}
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RVVCALL(OPFVV2, vfwsub_wv_h, WOP_WUUU_H, H4, H2, H2, vfwsubw16)
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RVVCALL(OPFVV2, vfwsub_wv_w, WOP_WUUU_W, H8, H4, H4, vfwsubw32)
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GEN_VEXT_VV_ENV(vfwsub_wv_h, 2, 4, clearl)
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GEN_VEXT_VV_ENV(vfwsub_wv_w, 4, 8, clearq)
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RVVCALL(OPFVF2, vfwsub_wf_h, WOP_WUUU_H, H4, H2, vfwsubw16)
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RVVCALL(OPFVF2, vfwsub_wf_w, WOP_WUUU_W, H8, H4, vfwsubw32)
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GEN_VEXT_VF(vfwsub_wf_h, 2, 4, clearl)
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GEN_VEXT_VF(vfwsub_wf_w, 4, 8, clearq)
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