mirror of https://gitee.com/openkylin/qemu.git
target/ppc: Put LPCR[GTSE] in hflags
Because this bit was not in hflags, the privilege check for tlb instructions was essentially random. Recompute hflags when storing to LPCR. Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210323184340.619757-7-richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -596,6 +596,7 @@ enum {
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HFLAGS_LE = 0, /* MSR_LE -- comes from elsewhere on 601 */
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HFLAGS_HV = 1, /* computed from MSR_HV and other state */
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HFLAGS_64 = 2, /* computed from MSR_CE and MSR_SF */
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HFLAGS_GTSE = 3, /* computed from SPR_LPCR[GTSE] */
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HFLAGS_DR = 4, /* MSR_DR */
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HFLAGS_IR = 5, /* MSR_IR */
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HFLAGS_SPE = 6, /* from MSR_SPE if cpu has SPE; avoid overlap w/ MSR_VR */
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@ -149,6 +149,9 @@ void hreg_compute_hflags(CPUPPCState *env)
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if ((ppc_flags & POWERPC_FLAG_TM) && (msr & (1ull << MSR_TM))) {
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hflags |= 1 << HFLAGS_TM;
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}
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if (env->spr[SPR_LPCR] & LPCR_GTSE) {
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hflags |= 1 << HFLAGS_GTSE;
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}
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#ifndef CONFIG_USER_ONLY
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if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) {
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@ -30,6 +30,7 @@
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#include "exec/log.h"
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#include "hw/hw.h"
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#include "mmu-book3s-v3.h"
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#include "helper_regs.h"
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/* #define DEBUG_SLB */
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@ -1125,6 +1126,8 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val)
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CPUPPCState *env = &cpu->env;
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env->spr[SPR_LPCR] = val & pcc->lpcr_mask;
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/* The gtse bit affects hflags */
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hreg_compute_hflags(env);
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}
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void helper_store_lpcr(CPUPPCState *env, target_ulong val)
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@ -7908,7 +7908,7 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
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ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1;
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ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1;
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ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1;
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ctx->gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE);
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ctx->gtse = (hflags >> HFLAGS_GTSE) & 1;
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ctx->singlestep_enabled = 0;
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if ((hflags >> HFLAGS_SE) & 1) {
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