mirror of https://gitee.com/openkylin/qemu.git
i.MX: add support for lower and upper interrupt in GPIO.
The i.MX6 GPIO device supports 2 interrupts instead of one. * 1 for the lower 16 GPIOs. * 1 for the upper 16 GPIOs. i.MX31 and i.MX25 only support 1 interrupt for the 32 GPIOs. So we add a property to turn the behavior on when required. Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 1447497668-1603-1-git-send-email-jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -62,7 +62,12 @@ static const char *imx_gpio_reg_name(uint32_t reg)
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static void imx_gpio_update_int(IMXGPIOState *s)
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{
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qemu_set_irq(s->irq, (s->isr & s->imr) ? 1 : 0);
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if (s->has_upper_pin_irq) {
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qemu_set_irq(s->irq[0], (s->isr & s->imr & 0x0000FFFF) ? 1 : 0);
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qemu_set_irq(s->irq[1], (s->isr & s->imr & 0xFFFF0000) ? 1 : 0);
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} else {
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qemu_set_irq(s->irq[0], (s->isr & s->imr) ? 1 : 0);
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}
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}
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static void imx_gpio_set_int_line(IMXGPIOState *s, int line, IMXGPIOLevel level)
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@ -282,6 +287,8 @@ static const VMStateDescription vmstate_imx_gpio = {
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static Property imx_gpio_properties[] = {
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DEFINE_PROP_BOOL("has-edge-sel", IMXGPIOState, has_edge_sel, true),
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DEFINE_PROP_BOOL("has-upper-pin-irq", IMXGPIOState, has_upper_pin_irq,
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false),
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DEFINE_PROP_END_OF_LIST(),
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};
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@ -311,7 +318,8 @@ static void imx_gpio_realize(DeviceState *dev, Error **errp)
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qdev_init_gpio_in(DEVICE(s), imx_gpio_set, IMX_GPIO_PIN_COUNT);
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qdev_init_gpio_out(DEVICE(s), s->output, IMX_GPIO_PIN_COUNT);
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sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
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sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[0]);
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sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[1]);
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sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
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}
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@ -54,8 +54,9 @@ typedef struct IMXGPIOState {
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uint32_t isr;
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bool has_edge_sel;
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uint32_t edge_sel;
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bool has_upper_pin_irq;
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qemu_irq irq;
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qemu_irq irq[2];
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qemu_irq output[IMX_GPIO_PIN_COUNT];
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} IMXGPIOState;
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