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target-arm queue: 

* refactor to use tcg_constant where appropriate
  * Advertise support for FEAT_TTL and FEAT_BBM level 2
  * smmuv3: Cache event fault record
  * smmuv3: Add space in guest error message
  * smmuv3: Advertise support for SMMUv3.2-BBML2
 -----BEGIN PGP SIGNATURE-----
 
 iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmJqpu4ZHHBldGVyLm1h
 eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3pOQD/9G190+ntJm4Vndz0I6bCDP
 svDrWwsioOJ4q5Pah6517JACkwN5sx0adMGyAeRC3Kcbz5B2141vv9hJOnJmLB1D
 l6KbH8XZaftC0B8fXsPkaH6XEdBHGz6YbOZaLOTwmFqF9d18OFW4d8+CAvfldZRc
 +DYeolEhoL9eLTS16BlXPxb0LajQHhbN1Xdu3t8CGh31C52ZrG4h8cus6YMEDjfA
 rfBthh/2QvVFmDedIfX4QrlImCTs+bTaSkhUBmX6qakWII0QykItgQTEZ8IHEr8/
 QmG+xlkP1MmffyHU3F4inEVXpjCSzula4ycZpNVGsrTHYxLBzsTSD+EzicLHMZSt
 64tQhLxPjAzC1MEHp7bJHyQXon7REWd6u1jPRlMWTGpZqbMMchBPjFrsxK3YPdvi
 a/8KIulXuX+GjzbOIHnpttIy+U0UrjTEyxjpk+Ay2iZ+U6+hA3i2ni++dzq9dYb6
 IiCl+o29r/7fNaWpG3b38kn9vpxjwAAw+qfwwSqyM+8/KMirgJ8rpEmUPei/h7fy
 vqpNlVxd1+Tzb3ljCXNRriZ05xo5I9LIb+dLAig1orENS7w3SzW/GnM+S7raOwQb
 u9mxNmbQJ1MhkjNC/6wzniBre6EBs31X2GIWeuiWe/js2YFPQC06b1WwIc/bYNUv
 anbECOS34mtxbExFfdlxUQ==
 =IPEn
 -----END PGP SIGNATURE-----

Merge tag 'pull-target-arm-20220428' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * refactor to use tcg_constant where appropriate
 * Advertise support for FEAT_TTL and FEAT_BBM level 2
 * smmuv3: Cache event fault record
 * smmuv3: Add space in guest error message
 * smmuv3: Advertise support for SMMUv3.2-BBML2

# -----BEGIN PGP SIGNATURE-----
#
# iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmJqpu4ZHHBldGVyLm1h
# eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3pOQD/9G190+ntJm4Vndz0I6bCDP
# svDrWwsioOJ4q5Pah6517JACkwN5sx0adMGyAeRC3Kcbz5B2141vv9hJOnJmLB1D
# l6KbH8XZaftC0B8fXsPkaH6XEdBHGz6YbOZaLOTwmFqF9d18OFW4d8+CAvfldZRc
# +DYeolEhoL9eLTS16BlXPxb0LajQHhbN1Xdu3t8CGh31C52ZrG4h8cus6YMEDjfA
# rfBthh/2QvVFmDedIfX4QrlImCTs+bTaSkhUBmX6qakWII0QykItgQTEZ8IHEr8/
# QmG+xlkP1MmffyHU3F4inEVXpjCSzula4ycZpNVGsrTHYxLBzsTSD+EzicLHMZSt
# 64tQhLxPjAzC1MEHp7bJHyQXon7REWd6u1jPRlMWTGpZqbMMchBPjFrsxK3YPdvi
# a/8KIulXuX+GjzbOIHnpttIy+U0UrjTEyxjpk+Ay2iZ+U6+hA3i2ni++dzq9dYb6
# IiCl+o29r/7fNaWpG3b38kn9vpxjwAAw+qfwwSqyM+8/KMirgJ8rpEmUPei/h7fy
# vqpNlVxd1+Tzb3ljCXNRriZ05xo5I9LIb+dLAig1orENS7w3SzW/GnM+S7raOwQb
# u9mxNmbQJ1MhkjNC/6wzniBre6EBs31X2GIWeuiWe/js2YFPQC06b1WwIc/bYNUv
# anbECOS34mtxbExFfdlxUQ==
# =IPEn
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 28 Apr 2022 07:38:38 AM PDT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]

* tag 'pull-target-arm-20220428' of https://git.linaro.org/people/pmaydell/qemu-arm: (54 commits)
  hw/arm/smmuv3: Advertise support for SMMUv3.2-BBML2
  target/arm: Advertise support for FEAT_BBM level 2
  target/arm: Advertise support for FEAT_TTL
  hw/arm/smmuv3: Add space in guest error message
  hw/arm/smmuv3: Cache event fault record
  target/arm: Use field names for accessing DBGWCRn
  target/arm: Disable cryptographic instructions when neon is disabled
  target/arm: Use tcg_constant for vector descriptor
  target/arm: Use tcg_constant for do_brk{2,3}
  target/arm: Use tcg_constant for predicate descriptors
  target/arm: Use tcg_constant in do_zzi_{sat, ool}, do_fp_imm
  target/arm: Use tcg_constant in SUBR
  target/arm: Use tcg_constant in LD1, ST1
  target/arm: Use tcg_constant in WHILE
  target/arm: Use tcg_constant in do_clast_scalar
  target/arm: Use tcg_constant in {incr, wrap}_last_active
  target/arm: Use tcg_constant in FCPY, CPY
  target/arm: Use tcg_constant in SINCDEC, INCDEC
  target/arm: Use tcg_constant for trans_INDEX_*
  target/arm: Use tcg_constant in trans_CSEL
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2022-04-28 08:34:17 -07:00
parent 6071ff6087 f8e7163d9e
commit f228336020
13 changed files with 293 additions and 531 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
docs/system/arm/emulation.rst
View File

@ -9,6 +9,7 @@ the following architecture extensions:
- FEAT_AA32HPD (AArch32 hierarchical permission disables)
- FEAT_AA32I8MM (AArch32 Int8 matrix multiplication instructions)
- FEAT_AES (AESD and AESE instructions)
- FEAT_BBM at level 2 (Translation table break-before-make levels)
- FEAT_BF16 (AArch64 BFloat16 instructions)
- FEAT_BTI (Branch Target Identification)
- FEAT_DIT (Data Independent Timing instructions)
@ -54,6 +55,7 @@ the following architecture extensions:
- FEAT_TLBIOS (TLB invalidate instructions in Outer Shareable domain)
- FEAT_TLBIRANGE (TLB invalidate range instructions)
- FEAT_TTCNP (Translation table Common not private translations)
- FEAT_TTL (Translation Table Level)
- FEAT_TTST (Small translation tables)
- FEAT_UAO (Unprivileged Access Override control)
- FEAT_VHE (Virtualization Host Extensions)

2
hw/arm/smmuv3-internal.h
View File

@ -56,6 +56,7 @@ REG32(IDR2, 0x8)
REG32(IDR3, 0xc)
FIELD(IDR3, HAD, 2, 1);
FIELD(IDR3, RIL, 10, 1);
FIELD(IDR3, BBML, 11, 2);
REG32(IDR4, 0x10)
REG32(IDR5, 0x14)
FIELD(IDR5, OAS, 0, 3);
@ -387,7 +388,6 @@ typedef struct SMMUEventInfo {
SMMUEventType type;
uint32_t sid;
bool recorded;
bool record_trans_faults;
bool inval_ste_allowed;
union {
struct {

17
hw/arm/smmuv3.c
View File

@ -259,6 +259,7 @@ static void smmuv3_init_regs(SMMUv3State *s)
s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, 1);
s->idr[3] = FIELD_DP32(s->idr[3], IDR3, HAD, 1);
s->idr[3] = FIELD_DP32(s->idr[3], IDR3, BBML, 2);
/* 4K, 16K and 64K granule support */
s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN4K, 1);
@ -527,7 +528,7 @@ static int decode_cd(SMMUTransCfg *cfg, CD *cd, SMMUEventInfo *event)
trace_smmuv3_decode_cd_tt(i, tt->tsz, tt->ttb, tt->granule_sz, tt->had);
}
event->record_trans_faults = CD_R(cd);
cfg->record_faults = CD_R(cd);
return 0;
@ -680,7 +681,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
tt = select_tt(cfg, addr);
if (!tt) {
if (event.record_trans_faults) {
if (cfg->record_faults) {
event.type = SMMU_EVT_F_TRANSLATION;
event.u.f_translation.addr = addr;
event.u.f_translation.rnw = flag & 0x1;
@ -696,7 +697,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
if (cached_entry) {
if ((flag & IOMMU_WO) && !(cached_entry->entry.perm & IOMMU_WO)) {
status = SMMU_TRANS_ERROR;
if (event.record_trans_faults) {
if (cfg->record_faults) {
event.type = SMMU_EVT_F_PERMISSION;
event.u.f_permission.addr = addr;
event.u.f_permission.rnw = flag & 0x1;
@ -720,28 +721,28 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
event.u.f_walk_eabt.addr2 = ptw_info.addr;
break;
case SMMU_PTW_ERR_TRANSLATION:
if (event.record_trans_faults) {
if (cfg->record_faults) {
event.type = SMMU_EVT_F_TRANSLATION;
event.u.f_translation.addr = addr;
event.u.f_translation.rnw = flag & 0x1;
}
break;
case SMMU_PTW_ERR_ADDR_SIZE:
if (event.record_trans_faults) {
if (cfg->record_faults) {
event.type = SMMU_EVT_F_ADDR_SIZE;
event.u.f_addr_size.addr = addr;
event.u.f_addr_size.rnw = flag & 0x1;
}
break;
case SMMU_PTW_ERR_ACCESS:
if (event.record_trans_faults) {
if (cfg->record_faults) {
event.type = SMMU_EVT_F_ACCESS;
event.u.f_access.addr = addr;
event.u.f_access.rnw = flag & 0x1;
}
break;
case SMMU_PTW_ERR_PERMISSION:
if (event.record_trans_faults) {
if (cfg->record_faults) {
event.type = SMMU_EVT_F_PERMISSION;
event.u.f_permission.addr = addr;
event.u.f_permission.rnw = flag & 0x1;
@ -786,7 +787,7 @@ epilogue:
break;
case SMMU_TRANS_ERROR:
qemu_log_mask(LOG_GUEST_ERROR,
"%s translation failed for iova=0x%"PRIx64"(%s)\n",
"%s translation failed for iova=0x%"PRIx64" (%s)\n",
mr->parent_obj.name, addr, smmu_event_string(event.type));
smmuv3_record_event(s, &event);
break;

1
include/hw/arm/smmu-common.h
View File

@ -71,6 +71,7 @@ typedef struct SMMUTransCfg {
bool disabled; /* smmu is disabled */
bool bypassed; /* translation is bypassed */
bool aborted; /* translation is aborted */
bool record_faults; /* record fault events */
uint64_t ttb; /* TT base address */
uint8_t oas; /* output address width */
uint8_t tbi; /* Top Byte Ignore */

9
target/arm/cpu.c
View File

@ -1587,6 +1587,12 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
unset_feature(env, ARM_FEATURE_NEON);
t = cpu->isar.id_aa64isar0;
t = FIELD_DP64(t, ID_AA64ISAR0, AES, 0);
t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0);
t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0);
t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 0);
t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 0);
t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 0);
t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0);
cpu->isar.id_aa64isar0 = t;
@ -1601,6 +1607,9 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
cpu->isar.id_aa64pfr0 = t;
u = cpu->isar.id_isar5;
u = FIELD_DP32(u, ID_ISAR5, AES, 0);
u = FIELD_DP32(u, ID_ISAR5, SHA1, 0);
u = FIELD_DP32(u, ID_ISAR5, SHA2, 0);
u = FIELD_DP32(u, ID_ISAR5, RDM, 0);
u = FIELD_DP32(u, ID_ISAR5, VCMA, 0);
cpu->isar.id_isar5 = u;

2
target/arm/cpu64.c
View File

@ -839,6 +839,8 @@ static void aarch64_max_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */
t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */
cpu->isar.id_aa64mmfr2 = t;
t = cpu->isar.id_aa64zfr0;

10
target/arm/debug_helper.c
View File

@ -143,9 +143,9 @@ static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp)
* Non-Secure to simplify the code slightly compared to the full
* table in the ARM ARM.
*/
pac = extract64(cr, 1, 2);
hmc = extract64(cr, 13, 1);
ssc = extract64(cr, 14, 2);
pac = FIELD_EX64(cr, DBGWCR, PAC);
hmc = FIELD_EX64(cr, DBGWCR, HMC);
ssc = FIELD_EX64(cr, DBGWCR, SSC);
switch (ssc) {
case 0:
@ -184,8 +184,8 @@ static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp)
g_assert_not_reached();
}
wt = extract64(cr, 20, 1);
lbn = extract64(cr, 16, 4);
wt = FIELD_EX64(cr, DBGWCR, WT);
lbn = FIELD_EX64(cr, DBGWCR, LBN);
if (wt && !linked_bp_matches(cpu, lbn)) {
return false;

8
target/arm/helper.c
View File

@ -6320,12 +6320,12 @@ void hw_watchpoint_update(ARMCPU *cpu, int n)
env->cpu_watchpoint[n] = NULL;
}
if (!extract64(wcr, 0, 1)) {
if (!FIELD_EX64(wcr, DBGWCR, E)) {
/* E bit clear : watchpoint disabled */
return;
}
switch (extract64(wcr, 3, 2)) {
switch (FIELD_EX64(wcr, DBGWCR, LSC)) {
case 0:
/* LSC 00 is reserved and must behave as if the wp is disabled */
return;
@ -6344,7 +6344,7 @@ void hw_watchpoint_update(ARMCPU *cpu, int n)
* CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
* thus generating a watchpoint for every byte in the masked region.
*/
mask = extract64(wcr, 24, 4);
mask = FIELD_EX64(wcr, DBGWCR, MASK);
if (mask == 1 || mask == 2) {
/* Reserved values of MASK; we must act as if the mask value was
* some non-reserved value, or as if the watchpoint were disabled.
@ -6361,7 +6361,7 @@ void hw_watchpoint_update(ARMCPU *cpu, int n)
wvr &= ~(len - 1);
} else {
/* Watchpoint covers bytes defined by the byte address select bits */
int bas = extract64(wcr, 5, 8);
int bas = FIELD_EX64(wcr, DBGWCR, BAS);
int basstart;
if (extract64(wvr, 2, 1)) {

12
target/arm/internals.h
View File

@ -81,6 +81,18 @@ FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */
*/
#define FNC_RETURN_MIN_MAGIC 0xfefffffe
/* Bit definitions for DBGWCRn and DBGWCRn_EL1 */
FIELD(DBGWCR, E, 0, 1)
FIELD(DBGWCR, PAC, 1, 2)
FIELD(DBGWCR, LSC, 3, 2)
FIELD(DBGWCR, BAS, 5, 8)
FIELD(DBGWCR, HMC, 13, 1)
FIELD(DBGWCR, SSC, 14, 2)
FIELD(DBGWCR, LBN, 16, 4)
FIELD(DBGWCR, WT, 20, 1)
FIELD(DBGWCR, MASK, 24, 5)
FIELD(DBGWCR, SSCE, 29, 1)
/* We use a few fake FSR values for internal purposes in M profile.
* M profile cores don't have A/R format FSRs, but currently our
* get_phys_addr() code assumes A/R profile and reports failures via

14
target/arm/kvm64.c
View File

@ -208,7 +208,7 @@ static int insert_hw_watchpoint(target_ulong addr,
target_ulong len, int type)
{
HWWatchpoint wp = {
.wcr = 1, /* E=1, enable */
.wcr = R_DBGWCR_E_MASK, /* E=1, enable */
.wvr = addr & (~0x7ULL),
.details = { .vaddr = addr, .len = len }
};
@ -221,19 +221,19 @@ static int insert_hw_watchpoint(target_ulong addr,
* HMC=0 SSC=0 PAC=3 will hit EL0 or EL1, any security state,
* valid whether EL3 is implemented or not
*/
wp.wcr = deposit32(wp.wcr, 1, 2, 3);
wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, PAC, 3);
switch (type) {
case GDB_WATCHPOINT_READ:
wp.wcr = deposit32(wp.wcr, 3, 2, 1);
wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, LSC, 1);
wp.details.flags = BP_MEM_READ;
break;
case GDB_WATCHPOINT_WRITE:
wp.wcr = deposit32(wp.wcr, 3, 2, 2);
wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, LSC, 2);
wp.details.flags = BP_MEM_WRITE;
break;
case GDB_WATCHPOINT_ACCESS:
wp.wcr = deposit32(wp.wcr, 3, 2, 3);
wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, LSC, 3);
wp.details.flags = BP_MEM_ACCESS;
break;
default:
@ -252,8 +252,8 @@ static int insert_hw_watchpoint(target_ulong addr,
int bits = ctz64(len);
wp.wvr &= ~((1 << bits) - 1);
wp.wcr = deposit32(wp.wcr, 24, 4, bits);
wp.wcr = deposit32(wp.wcr, 5, 8, 0xff);
wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, MASK, bits);
wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, BAS, 0xff);
} else {
return -ENOBUFS;
}

301
target/arm/translate-a64.c
View File

@ -240,14 +240,10 @@ static void gen_address_with_allocation_tag0(TCGv_i64 dst, TCGv_i64 src)
static void gen_probe_access(DisasContext *s, TCGv_i64 ptr,
MMUAccessType acc, int log2_size)
{
TCGv_i32 t_acc = tcg_const_i32(acc);
TCGv_i32 t_idx = tcg_const_i32(get_mem_index(s));
TCGv_i32 t_size = tcg_const_i32(1 << log2_size);
gen_helper_probe_access(cpu_env, ptr, t_acc, t_idx, t_size);
tcg_temp_free_i32(t_acc);
tcg_temp_free_i32(t_idx);
tcg_temp_free_i32(t_size);
gen_helper_probe_access(cpu_env, ptr,
tcg_constant_i32(acc),
tcg_constant_i32(get_mem_index(s)),
tcg_constant_i32(1 << log2_size));
}
/*
@ -262,7 +258,6 @@ static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s, TCGv_i64 addr,
int core_idx)
{
if (tag_checked && s->mte_active[is_unpriv]) {
TCGv_i32 tcg_desc;
TCGv_i64 ret;
int desc = 0;
@ -271,11 +266,9 @@ static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s, TCGv_i64 addr,
desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << log2_size) - 1);
tcg_desc = tcg_const_i32(desc);
ret = new_tmp_a64(s);
gen_helper_mte_check(ret, cpu_env, tcg_desc, addr);
tcg_temp_free_i32(tcg_desc);
gen_helper_mte_check(ret, cpu_env, tcg_constant_i32(desc), addr);
return ret;
}
@ -296,7 +289,6 @@ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write,
bool tag_checked, int size)
{
if (tag_checked && s->mte_active[0]) {
TCGv_i32 tcg_desc;
TCGv_i64 ret;
int desc = 0;
@ -305,11 +297,9 @@ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write,
desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
desc = FIELD_DP32(desc, MTEDESC, SIZEM1, size - 1);
tcg_desc = tcg_const_i32(desc);
ret = new_tmp_a64(s);
gen_helper_mte_check(ret, cpu_env, tcg_desc, addr);
tcg_temp_free_i32(tcg_desc);
gen_helper_mte_check(ret, cpu_env, tcg_constant_i32(desc), addr);
return ret;
}
@ -348,11 +338,8 @@ static void gen_rebuild_hflags(DisasContext *s)
static void gen_exception_internal(int excp)
{
TCGv_i32 tcg_excp = tcg_const_i32(excp);
assert(excp_is_internal(excp));
gen_helper_exception_internal(cpu_env, tcg_excp);
tcg_temp_free_i32(tcg_excp);
gen_helper_exception_internal(cpu_env, tcg_constant_i32(excp));
}
static void gen_exception_internal_insn(DisasContext *s, uint64_t pc, int excp)
@ -364,12 +351,8 @@ static void gen_exception_internal_insn(DisasContext *s, uint64_t pc, int excp)
static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syndrome)
{
TCGv_i32 tcg_syn;
gen_a64_set_pc_im(s->pc_curr);
tcg_syn = tcg_const_i32(syndrome);
gen_helper_exception_bkpt_insn(cpu_env, tcg_syn);
tcg_temp_free_i32(tcg_syn);
gen_helper_exception_bkpt_insn(cpu_env, tcg_constant_i32(syndrome));
s->base.is_jmp = DISAS_NORETURN;
}
@ -831,15 +814,15 @@ static void gen_adc(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
static void gen_adc_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
{
if (sf) {
TCGv_i64 result, cf_64, vf_64, tmp;
result = tcg_temp_new_i64();
cf_64 = tcg_temp_new_i64();
vf_64 = tcg_temp_new_i64();
tmp = tcg_const_i64(0);
TCGv_i64 result = tcg_temp_new_i64();
TCGv_i64 cf_64 = tcg_temp_new_i64();
TCGv_i64 vf_64 = tcg_temp_new_i64();
TCGv_i64 tmp = tcg_temp_new_i64();
TCGv_i64 zero = tcg_constant_i64(0);
tcg_gen_extu_i32_i64(cf_64, cpu_CF);
tcg_gen_add2_i64(result, cf_64, t0, tmp, cf_64, tmp);
tcg_gen_add2_i64(result, cf_64, result, cf_64, t1, tmp);
tcg_gen_add2_i64(result, cf_64, t0, zero, cf_64, zero);
tcg_gen_add2_i64(result, cf_64, result, cf_64, t1, zero);
tcg_gen_extrl_i64_i32(cpu_CF, cf_64);
gen_set_NZ64(result);
@ -855,15 +838,15 @@ static void gen_adc_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
tcg_temp_free_i64(cf_64);
tcg_temp_free_i64(result);
} else {
TCGv_i32 t0_32, t1_32, tmp;
t0_32 = tcg_temp_new_i32();
t1_32 = tcg_temp_new_i32();
tmp = tcg_const_i32(0);
TCGv_i32 t0_32 = tcg_temp_new_i32();
TCGv_i32 t1_32 = tcg_temp_new_i32();
TCGv_i32 tmp = tcg_temp_new_i32();
TCGv_i32 zero = tcg_constant_i32(0);
tcg_gen_extrl_i64_i32(t0_32, t0);
tcg_gen_extrl_i64_i32(t1_32, t1);
tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, cpu_CF, tmp);
tcg_gen_add2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1_32, tmp);
tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, zero, cpu_CF, zero);
tcg_gen_add2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1_32, zero);
tcg_gen_mov_i32(cpu_ZF, cpu_NF);
tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32);
@ -1632,7 +1615,6 @@ static void gen_axflag(void)
static void handle_msr_i(DisasContext *s, uint32_t insn,
unsigned int op1, unsigned int op2, unsigned int crm)
{
TCGv_i32 t1;
int op = op1 << 3 | op2;
/* End the TB by default, chaining is ok. */
@ -1691,9 +1673,7 @@ static void handle_msr_i(DisasContext *s, uint32_t insn,
if (s->current_el == 0) {
goto do_unallocated;
}
t1 = tcg_const_i32(crm & PSTATE_SP);
gen_helper_msr_i_spsel(cpu_env, t1);
tcg_temp_free_i32(t1);
gen_helper_msr_i_spsel(cpu_env, tcg_constant_i32(crm & PSTATE_SP));
break;
case 0x19: /* SSBS */
@ -1721,15 +1701,11 @@ static void handle_msr_i(DisasContext *s, uint32_t insn,
break;
case 0x1e: /* DAIFSet */
t1 = tcg_const_i32(crm);
gen_helper_msr_i_daifset(cpu_env, t1);
tcg_temp_free_i32(t1);
gen_helper_msr_i_daifset(cpu_env, tcg_constant_i32(crm));
break;
case 0x1f: /* DAIFClear */
t1 = tcg_const_i32(crm);
gen_helper_msr_i_daifclear(cpu_env, t1);
tcg_temp_free_i32(t1);
gen_helper_msr_i_daifclear(cpu_env, tcg_constant_i32(crm));
/* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
s->base.is_jmp = DISAS_UPDATE_EXIT;
break;
@ -1842,19 +1818,14 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
/* Emit code to perform further access permissions checks at
* runtime; this may result in an exception.
*/
TCGv_ptr tmpptr;
TCGv_i32 tcg_syn, tcg_isread;
uint32_t syndrome;
gen_a64_set_pc_im(s->pc_curr);
tmpptr = tcg_const_ptr(ri);
syndrome = syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isread);
tcg_syn = tcg_const_i32(syndrome);
tcg_isread = tcg_const_i32(isread);
gen_helper_access_check_cp_reg(cpu_env, tmpptr, tcg_syn, tcg_isread);
tcg_temp_free_ptr(tmpptr);
tcg_temp_free_i32(tcg_syn);
tcg_temp_free_i32(tcg_isread);
gen_a64_set_pc_im(s->pc_curr);
gen_helper_access_check_cp_reg(cpu_env,
tcg_constant_ptr(ri),
tcg_constant_i32(syndrome),
tcg_constant_i32(isread));
} else if (ri->type & ARM_CP_RAISES_EXC) {
/*
* The readfn or writefn might raise an exception;
@ -1885,17 +1856,15 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
case ARM_CP_DC_ZVA:
/* Writes clear the aligned block of memory which rt points into. */
if (s->mte_active[0]) {
TCGv_i32 t_desc;
int desc = 0;
desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
t_desc = tcg_const_i32(desc);
tcg_rt = new_tmp_a64(s);
gen_helper_mte_check_zva(tcg_rt, cpu_env, t_desc, cpu_reg(s, rt));
tcg_temp_free_i32(t_desc);
gen_helper_mte_check_zva(tcg_rt, cpu_env,
tcg_constant_i32(desc), cpu_reg(s, rt));
} else {
tcg_rt = clean_data_tbi(s, cpu_reg(s, rt));
}
@ -1959,10 +1928,7 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
if (ri->type & ARM_CP_CONST) {
tcg_gen_movi_i64(tcg_rt, ri->resetvalue);
} else if (ri->readfn) {
TCGv_ptr tmpptr;
tmpptr = tcg_const_ptr(ri);
gen_helper_get_cp_reg64(tcg_rt, cpu_env, tmpptr);
tcg_temp_free_ptr(tmpptr);
gen_helper_get_cp_reg64(tcg_rt, cpu_env, tcg_constant_ptr(ri));
} else {
tcg_gen_ld_i64(tcg_rt, cpu_env, ri->fieldoffset);
}
@ -1971,10 +1937,7 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
/* If not forbidden by access permissions, treat as WI */
return;
} else if (ri->writefn) {
TCGv_ptr tmpptr;
tmpptr = tcg_const_ptr(ri);
gen_helper_set_cp_reg64(cpu_env, tmpptr, tcg_rt);
tcg_temp_free_ptr(tmpptr);
gen_helper_set_cp_reg64(cpu_env, tcg_constant_ptr(ri), tcg_rt);
} else {
tcg_gen_st_i64(tcg_rt, cpu_env, ri->fieldoffset);
}
@ -2052,7 +2015,6 @@ static void disas_exc(DisasContext *s, uint32_t insn)
int opc = extract32(insn, 21, 3);
int op2_ll = extract32(insn, 0, 5);
int imm16 = extract32(insn, 5, 16);
TCGv_i32 tmp;
switch (opc) {
case 0:
@ -2087,9 +2049,7 @@ static void disas_exc(DisasContext *s, uint32_t insn)
break;
}
gen_a64_set_pc_im(s->pc_curr);
tmp = tcg_const_i32(syn_aa64_smc(imm16));
gen_helper_pre_smc(cpu_env, tmp);
tcg_temp_free_i32(tmp);
gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa64_smc(imm16)));
gen_ss_advance(s);
gen_exception_insn(s, s->base.pc_next, EXCP_SMC,
syn_aa64_smc(imm16), 3);
@ -2563,7 +2523,7 @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt,
tcg_temp_free_i64(cmp);
} else if (tb_cflags(s->base.tb) & CF_PARALLEL) {
if (HAVE_CMPXCHG128) {
TCGv_i32 tcg_rs = tcg_const_i32(rs);
TCGv_i32 tcg_rs = tcg_constant_i32(rs);
if (s->be_data == MO_LE) {
gen_helper_casp_le_parallel(cpu_env, tcg_rs,
clean_addr, t1, t2);
@ -2571,7 +2531,6 @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt,
gen_helper_casp_be_parallel(cpu_env, tcg_rs,
clean_addr, t1, t2);
}
tcg_temp_free_i32(tcg_rs);
} else {
gen_helper_exit_atomic(cpu_env);
s->base.is_jmp = DISAS_NORETURN;
@ -2582,7 +2541,7 @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt,
TCGv_i64 a2 = tcg_temp_new_i64();
TCGv_i64 c1 = tcg_temp_new_i64();
TCGv_i64 c2 = tcg_temp_new_i64();
TCGv_i64 zero = tcg_const_i64(0);
TCGv_i64 zero = tcg_constant_i64(0);
/* Load the two words, in memory order. */
tcg_gen_qemu_ld_i64(d1, clean_addr, memidx,
@ -2603,7 +2562,6 @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt,
tcg_temp_free_i64(a2);
tcg_temp_free_i64(c1);
tcg_temp_free_i64(c2);
tcg_temp_free_i64(zero);
/* Write back the data from memory to Rs. */
tcg_gen_mov_i64(s1, d1);
@ -2820,7 +2778,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
tcg_rt = cpu_reg(s, rt);
clean_addr = tcg_const_i64(s->pc_curr + imm);
clean_addr = tcg_constant_i64(s->pc_curr + imm);
if (is_vector) {
do_fp_ld(s, rt, clean_addr, size);
} else {
@ -2830,7 +2788,6 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
do_gpr_ld(s, tcg_rt, clean_addr, size + is_signed * MO_SIGN,
false, true, rt, iss_sf, false);
}
tcg_temp_free_i64(clean_addr);
}
/*
@ -3736,7 +3693,7 @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
mop = endian | size | align;
elements = (is_q ? 16 : 8) >> size;
tcg_ebytes = tcg_const_i64(1 << size);
tcg_ebytes = tcg_constant_i64(1 << size);
for (r = 0; r < rpt; r++) {
int e;
for (e = 0; e < elements; e++) {
@ -3752,7 +3709,6 @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
}
}
}
tcg_temp_free_i64(tcg_ebytes);
if (!is_store) {
/* For non-quad operations, setting a slice of the low
@ -3882,7 +3838,7 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
total);
mop = finalize_memop(s, scale);
tcg_ebytes = tcg_const_i64(1 << scale);
tcg_ebytes = tcg_constant_i64(1 << scale);
for (xs = 0; xs < selem; xs++) {
if (replicate) {
/* Load and replicate to all elements */
@ -3904,7 +3860,6 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes);
rt = (rt + 1) % 32;
}
tcg_temp_free_i64(tcg_ebytes);
if (is_postidx) {
if (rm == 31) {
@ -4095,7 +4050,7 @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn)
if (is_zero) {
TCGv_i64 clean_addr = clean_data_tbi(s, addr);
TCGv_i64 tcg_zero = tcg_const_i64(0);
TCGv_i64 tcg_zero = tcg_constant_i64(0);
int mem_index = get_mem_index(s);
int i, n = (1 + is_pair) << LOG2_TAG_GRANULE;
@ -4105,7 +4060,6 @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn)
tcg_gen_addi_i64(clean_addr, clean_addr, 8);
tcg_gen_qemu_st_i64(tcg_zero, clean_addr, mem_index, MO_UQ);
}
tcg_temp_free_i64(tcg_zero);
}
if (index != 0) {
@ -4224,13 +4178,12 @@ static void disas_add_sub_imm(DisasContext *s, uint32_t insn)
tcg_gen_addi_i64(tcg_result, tcg_rn, imm);
}
} else {
TCGv_i64 tcg_imm = tcg_const_i64(imm);
TCGv_i64 tcg_imm = tcg_constant_i64(imm);
if (sub_op) {
gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm);
} else {
gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm);
}
tcg_temp_free_i64(tcg_imm);
}
if (is_64bit) {
@ -4278,12 +4231,9 @@ static void disas_add_sub_imm_with_tags(DisasContext *s, uint32_t insn)
tcg_rd = cpu_reg_sp(s, rd);
if (s->ata) {
TCGv_i32 offset = tcg_const_i32(imm);
TCGv_i32 tag_offset = tcg_const_i32(uimm4);
gen_helper_addsubg(tcg_rd, cpu_env, tcg_rn, offset, tag_offset);
tcg_temp_free_i32(tag_offset);
tcg_temp_free_i32(offset);
gen_helper_addsubg(tcg_rd, cpu_env, tcg_rn,
tcg_constant_i32(imm),
tcg_constant_i32(uimm4));
} else {
tcg_gen_addi_i64(tcg_rd, tcg_rn, imm);
gen_address_with_allocation_tag0(tcg_rd, tcg_rd);
@ -4469,7 +4419,6 @@ static void disas_movw_imm(DisasContext *s, uint32_t insn)
int opc = extract32(insn, 29, 2);
int pos = extract32(insn, 21, 2) << 4;
TCGv_i64 tcg_rd = cpu_reg(s, rd);
TCGv_i64 tcg_imm;
if (!sf && (pos >= 32)) {
unallocated_encoding(s);
@ -4489,9 +4438,7 @@ static void disas_movw_imm(DisasContext *s, uint32_t insn)
tcg_gen_movi_i64(tcg_rd, imm);
break;
case 3: /* MOVK */
tcg_imm = tcg_const_i64(imm);
tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_imm, pos, 16);
tcg_temp_free_i64(tcg_imm);
tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_constant_i64(imm), pos, 16);
if (!sf) {
tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
}
@ -4731,11 +4678,7 @@ static void shift_reg_imm(TCGv_i64 dst, TCGv_i64 src, int sf,
if (shift_i == 0) {
tcg_gen_mov_i64(dst, src);
} else {
TCGv_i64 shift_const;
shift_const = tcg_const_i64(shift_i);
shift_reg(dst, src, sf, shift_type, shift_const);
tcg_temp_free_i64(shift_const);
shift_reg(dst, src, sf, shift_type, tcg_constant_i64(shift_i));
}
}
@ -5312,7 +5255,7 @@ static void disas_cond_select(DisasContext *s, uint32_t insn)
tcg_rd = cpu_reg(s, rd);
a64_test_cc(&c, cond);
zero = tcg_const_i64(0);
zero = tcg_constant_i64(0);
if (rn == 31 && rm == 31 && (else_inc ^ else_inv)) {
/* CSET & CSETM. */
@ -5333,7 +5276,6 @@ static void disas_cond_select(DisasContext *s, uint32_t insn)
tcg_gen_movcond_i64(c.cond, tcg_rd, c.value, zero, t_true, t_false);
}
tcg_temp_free_i64(zero);
a64_free_cc(&c);
if (!sf) {
@ -5430,7 +5372,7 @@ static void handle_rev16(DisasContext *s, unsigned int sf,
TCGv_i64 tcg_rd = cpu_reg(s, rd);
TCGv_i64 tcg_tmp = tcg_temp_new_i64();
TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf);
TCGv_i64 mask = tcg_const_i64(sf ? 0x00ff00ff00ff00ffull : 0x00ff00ff);
TCGv_i64 mask = tcg_constant_i64(sf ? 0x00ff00ff00ff00ffull : 0x00ff00ff);
tcg_gen_shri_i64(tcg_tmp, tcg_rn, 8);
tcg_gen_and_i64(tcg_rd, tcg_rn, mask);
@ -5438,7 +5380,6 @@ static void handle_rev16(DisasContext *s, unsigned int sf,
tcg_gen_shli_i64(tcg_rd, tcg_rd, 8);
tcg_gen_or_i64(tcg_rd, tcg_rd, tcg_tmp);
tcg_temp_free_i64(mask);
tcg_temp_free_i64(tcg_tmp);
}
@ -5721,15 +5662,13 @@ static void handle_crc32(DisasContext *s,
}
tcg_acc = cpu_reg(s, rn);
tcg_bytes = tcg_const_i32(1 << sz);
tcg_bytes = tcg_constant_i32(1 << sz);
if (crc32c) {
gen_helper_crc32c_64(cpu_reg(s, rd), tcg_acc, tcg_val, tcg_bytes);
} else {
gen_helper_crc32_64(cpu_reg(s, rd), tcg_acc, tcg_val, tcg_bytes);
}
tcg_temp_free_i32(tcg_bytes);
}
/* Data-processing (2 source)
@ -5795,15 +5734,13 @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) {
goto do_unallocated;
} else {
TCGv_i64 t1 = tcg_const_i64(1);
TCGv_i64 t2 = tcg_temp_new_i64();
TCGv_i64 t = tcg_temp_new_i64();
tcg_gen_extract_i64(t2, cpu_reg_sp(s, rn), 56, 4);
tcg_gen_shl_i64(t1, t1, t2);
tcg_gen_or_i64(cpu_reg(s, rd), cpu_reg(s, rm), t1);
tcg_gen_extract_i64(t, cpu_reg_sp(s, rn), 56, 4);
tcg_gen_shl_i64(t, tcg_constant_i64(1), t);
tcg_gen_or_i64(cpu_reg(s, rd), cpu_reg(s, rm), t);
tcg_temp_free_i64(t1);
tcg_temp_free_i64(t2);
tcg_temp_free_i64(t);
}
break;
case 8: /* LSLV */
@ -5938,7 +5875,7 @@ static void handle_fp_compare(DisasContext *s, int size,
tcg_vn = read_fp_dreg(s, rn);
if (cmp_with_zero) {
tcg_vm = tcg_const_i64(0);
tcg_vm = tcg_constant_i64(0);
} else {
tcg_vm = read_fp_dreg(s, rm);
}
@ -6048,7 +5985,6 @@ static void disas_fp_compare(DisasContext *s, uint32_t insn)
static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
{
unsigned int mos, type, rm, cond, rn, op, nzcv;
TCGv_i64 tcg_flags;
TCGLabel *label_continue = NULL;
int size;
@ -6092,9 +6028,7 @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
label_continue = gen_new_label();
arm_gen_test_cc(cond, label_match);
/* nomatch: */
tcg_flags = tcg_const_i64(nzcv << 28);
gen_set_nzcv(tcg_flags);
tcg_temp_free_i64(tcg_flags);
gen_set_nzcv(tcg_constant_i64(nzcv << 28));
tcg_gen_br(label_continue);
gen_set_label(label_match);
}
@ -6115,7 +6049,7 @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
static void disas_fp_csel(DisasContext *s, uint32_t insn)
{
unsigned int mos, type, rm, cond, rn, rd;
TCGv_i64 t_true, t_false, t_zero;
TCGv_i64 t_true, t_false;
DisasCompare64 c;
MemOp sz;
@ -6160,9 +6094,8 @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
read_vec_element(s, t_false, rm, 0, sz);
a64_test_cc(&c, cond);
t_zero = tcg_const_i64(0);
tcg_gen_movcond_i64(c.cond, t_true, c.value, t_zero, t_true, t_false);
tcg_temp_free_i64(t_zero);
tcg_gen_movcond_i64(c.cond, t_true, c.value, tcg_constant_i64(0),
t_true, t_false);
tcg_temp_free_i64(t_false);
a64_free_cc(&c);
@ -6944,7 +6877,6 @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)
int type = extract32(insn, 22, 2);
int mos = extract32(insn, 29, 3);
uint64_t imm;
TCGv_i64 tcg_res;
MemOp sz;
if (mos || imm5) {
@ -6975,10 +6907,7 @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)
}
imm = vfp_expand_imm(sz, imm8);
tcg_res = tcg_const_i64(imm);
write_fp_dreg(s, rd, tcg_res);
tcg_temp_free_i64(tcg_res);
write_fp_dreg(s, rd, tcg_constant_i64(imm));
}
/* Handle floating point <=> fixed point conversions. Note that we can
@ -6996,7 +6925,7 @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
tcg_fpstatus = fpstatus_ptr(type == 3 ? FPST_FPCR_F16 : FPST_FPCR);
tcg_shift = tcg_const_i32(64 - scale);
tcg_shift = tcg_constant_i32(64 - scale);
if (itof) {
TCGv_i64 tcg_int = cpu_reg(s, rn);
@ -7155,7 +7084,6 @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
}
tcg_temp_free_ptr(tcg_fpstatus);
tcg_temp_free_i32(tcg_shift);
}
/* Floating point <-> fixed point conversions
@ -8426,7 +8354,7 @@ static void handle_shri_with_rndacc(TCGv_i64 tcg_res, TCGv_i64 tcg_src,
/* Deal with the rounding step */
if (round) {
if (extended_result) {
TCGv_i64 tcg_zero = tcg_const_i64(0);
TCGv_i64 tcg_zero = tcg_constant_i64(0);
if (!is_u) {
/* take care of sign extending tcg_res */
tcg_gen_sari_i64(tcg_src_hi, tcg_src, 63);
@ -8438,7 +8366,6 @@ static void handle_shri_with_rndacc(TCGv_i64 tcg_res, TCGv_i64 tcg_src,
tcg_src, tcg_zero,
tcg_rnd, tcg_zero);
}
tcg_temp_free_i64(tcg_zero);
} else {
tcg_gen_add_i64(tcg_src, tcg_src, tcg_rnd);
}
@ -8524,8 +8451,7 @@ static void handle_scalar_simd_shri(DisasContext *s,
}
if (round) {
uint64_t round_const = 1ULL << (shift - 1);
tcg_round = tcg_const_i64(round_const);
tcg_round = tcg_constant_i64(1ULL << (shift - 1));
} else {
tcg_round = NULL;
}
@ -8551,9 +8477,6 @@ static void handle_scalar_simd_shri(DisasContext *s,
tcg_temp_free_i64(tcg_rn);
tcg_temp_free_i64(tcg_rd);
if (round) {
tcg_temp_free_i64(tcg_round);
}
}
/* SHL/SLI - Scalar shift left */
@ -8651,8 +8574,7 @@ static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q,
tcg_final = tcg_const_i64(0);
if (round) {
uint64_t round_const = 1ULL << (shift - 1);
tcg_round = tcg_const_i64(round_const);
tcg_round = tcg_constant_i64(1ULL << (shift - 1));
} else {
tcg_round = NULL;
}
@ -8672,9 +8594,6 @@ static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q,
write_vec_element(s, tcg_final, rd, 1, MO_64);
}
if (round) {
tcg_temp_free_i64(tcg_round);
}
tcg_temp_free_i64(tcg_rn);
tcg_temp_free_i64(tcg_rd);
tcg_temp_free_i32(tcg_rd_narrowed);
@ -8726,7 +8645,7 @@ static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q,
}
if (size == 3) {
TCGv_i64 tcg_shift = tcg_const_i64(shift);
TCGv_i64 tcg_shift = tcg_constant_i64(shift);
static NeonGenTwo64OpEnvFn * const fns[2][2] = {
{ gen_helper_neon_qshl_s64, gen_helper_neon_qshlu_s64 },
{ NULL, gen_helper_neon_qshl_u64 },
@ -8743,10 +8662,9 @@ static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q,
tcg_temp_free_i64(tcg_op);
}
tcg_temp_free_i64(tcg_shift);
clear_vec_high(s, is_q, rd);
} else {
TCGv_i32 tcg_shift = tcg_const_i32(shift);
TCGv_i32 tcg_shift = tcg_constant_i32(shift);
static NeonGenTwoOpEnvFn * const fns[2][2][3] = {
{
{ gen_helper_neon_qshl_s8,
@ -8791,7 +8709,6 @@ static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q,
tcg_temp_free_i32(tcg_op);
}
tcg_temp_free_i32(tcg_shift);
if (!scalar) {
clear_vec_high(s, is_q, rd);
@ -8811,7 +8728,7 @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
int pass;
if (fracbits || size == MO_64) {
tcg_shift = tcg_const_i32(fracbits);
tcg_shift = tcg_constant_i32(fracbits);
}
if (size == MO_64) {
@ -8896,9 +8813,6 @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
}
tcg_temp_free_ptr(tcg_fpst);
if (tcg_shift) {
tcg_temp_free_i32(tcg_shift);
}
clear_vec_high(s, elements << size == 16, rd);
}
@ -8988,7 +8902,7 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
tcg_fpstatus = fpstatus_ptr(size == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
fracbits = (16 << size) - immhb;
tcg_shift = tcg_const_i32(fracbits);
tcg_shift = tcg_constant_i32(fracbits);
if (size == MO_64) {
int maxpass = is_scalar ? 1 : 2;
@ -9046,7 +8960,6 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
}
}
tcg_temp_free_i32(tcg_shift);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
tcg_temp_free_ptr(tcg_fpstatus);
tcg_temp_free_i32(tcg_rmode);
@ -9918,23 +9831,15 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
case 0x1c: /* FCVTAS */
case 0x3a: /* FCVTPS */
case 0x3b: /* FCVTZS */
{
TCGv_i32 tcg_shift = tcg_const_i32(0);
gen_helper_vfp_tosqd(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus);
tcg_temp_free_i32(tcg_shift);
gen_helper_vfp_tosqd(tcg_rd, tcg_rn, tcg_constant_i32(0), tcg_fpstatus);
break;
}
case 0x5a: /* FCVTNU */
case 0x5b: /* FCVTMU */
case 0x5c: /* FCVTAU */
case 0x7a: /* FCVTPU */
case 0x7b: /* FCVTZU */
{
TCGv_i32 tcg_shift = tcg_const_i32(0);
gen_helper_vfp_touqd(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus);
tcg_temp_free_i32(tcg_shift);
gen_helper_vfp_touqd(tcg_rd, tcg_rn, tcg_constant_i32(0), tcg_fpstatus);
break;
}
case 0x18: /* FRINTN */
case 0x19: /* FRINTM */
case 0x38: /* FRINTP */
@ -9974,7 +9879,7 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
if (is_double) {
TCGv_i64 tcg_op = tcg_temp_new_i64();
TCGv_i64 tcg_zero = tcg_const_i64(0);
TCGv_i64 tcg_zero = tcg_constant_i64(0);
TCGv_i64 tcg_res = tcg_temp_new_i64();
NeonGenTwoDoubleOpFn *genfn;
bool swap = false;
@ -10010,13 +9915,12 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
write_vec_element(s, tcg_res, rd, pass, MO_64);
}
tcg_temp_free_i64(tcg_res);
tcg_temp_free_i64(tcg_zero);
tcg_temp_free_i64(tcg_op);
clear_vec_high(s, !is_scalar, rd);
} else {
TCGv_i32 tcg_op = tcg_temp_new_i32();
TCGv_i32 tcg_zero = tcg_const_i32(0);
TCGv_i32 tcg_zero = tcg_constant_i32(0);
TCGv_i32 tcg_res = tcg_temp_new_i32();
NeonGenTwoSingleOpFn *genfn;
bool swap = false;
@ -10085,7 +9989,6 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
}
}
tcg_temp_free_i32(tcg_res);
tcg_temp_free_i32(tcg_zero);
tcg_temp_free_i32(tcg_op);
if (!is_scalar) {
clear_vec_high(s, is_q, rd);
@ -10186,7 +10089,7 @@ static void handle_2misc_narrow(DisasContext *s, bool scalar,
int passes = scalar ? 1 : 2;
if (scalar) {
tcg_res[1] = tcg_const_i32(0);
tcg_res[1] = tcg_constant_i32(0);
}
for (pass = 0; pass < passes; pass++) {
@ -10364,9 +10267,7 @@ static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u,
}
if (is_scalar) {
TCGv_i64 tcg_zero = tcg_const_i64(0);
write_vec_element(s, tcg_zero, rd, 0, MO_64);
tcg_temp_free_i64(tcg_zero);
write_vec_element(s, tcg_constant_i64(0), rd, 0, MO_64);
}
write_vec_element_i32(s, tcg_rd, rd, pass, MO_32);
}
@ -10549,23 +10450,17 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
case 0x1c: /* FCVTAS */
case 0x3a: /* FCVTPS */
case 0x3b: /* FCVTZS */
{
TCGv_i32 tcg_shift = tcg_const_i32(0);
gen_helper_vfp_tosls(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus);
tcg_temp_free_i32(tcg_shift);
gen_helper_vfp_tosls(tcg_rd, tcg_rn, tcg_constant_i32(0),
tcg_fpstatus);
break;
}
case 0x5a: /* FCVTNU */
case 0x5b: /* FCVTMU */
case 0x5c: /* FCVTAU */
case 0x7a: /* FCVTPU */
case 0x7b: /* FCVTZU */
{
TCGv_i32 tcg_shift = tcg_const_i32(0);
gen_helper_vfp_touls(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus);
tcg_temp_free_i32(tcg_shift);
gen_helper_vfp_touls(tcg_rd, tcg_rn, tcg_constant_i32(0),
tcg_fpstatus);
break;
}
default:
g_assert_not_reached();
}
@ -10737,8 +10632,7 @@ static void handle_vec_simd_shrn(DisasContext *s, bool is_q,
read_vec_element(s, tcg_final, rd, is_q ? 1 : 0, MO_64);
if (round) {
uint64_t round_const = 1ULL << (shift - 1);
tcg_round = tcg_const_i64(round_const);
tcg_round = tcg_constant_i64(1ULL << (shift - 1));
} else {
tcg_round = NULL;
}
@ -10756,9 +10650,6 @@ static void handle_vec_simd_shrn(DisasContext *s, bool is_q,
} else {
write_vec_element(s, tcg_final, rd, 1, MO_64);
}
if (round) {
tcg_temp_free_i64(tcg_round);
}
tcg_temp_free_i64(tcg_rn);
tcg_temp_free_i64(tcg_rd);
tcg_temp_free_i64(tcg_final);
@ -12462,7 +12353,7 @@ static void handle_2misc_pairwise(DisasContext *s, int opcode, bool u,
}
}
if (!is_q) {
tcg_res[1] = tcg_const_i64(0);
tcg_res[1] = tcg_constant_i64(0);
}
for (pass = 0; pass < 2; pass++) {
write_vec_element(s, tcg_res[pass], rd, pass, MO_64);
@ -12895,25 +12786,17 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
case 0x1c: /* FCVTAS */
case 0x3a: /* FCVTPS */
case 0x3b: /* FCVTZS */
{
TCGv_i32 tcg_shift = tcg_const_i32(0);
gen_helper_vfp_tosls(tcg_res, tcg_op,
tcg_shift, tcg_fpstatus);
tcg_temp_free_i32(tcg_shift);
tcg_constant_i32(0), tcg_fpstatus);
break;
}
case 0x5a: /* FCVTNU */
case 0x5b: /* FCVTMU */
case 0x5c: /* FCVTAU */
case 0x7a: /* FCVTPU */
case 0x7b: /* FCVTZU */
{
TCGv_i32 tcg_shift = tcg_const_i32(0);
gen_helper_vfp_touls(tcg_res, tcg_op,
tcg_shift, tcg_fpstatus);
tcg_temp_free_i32(tcg_shift);
tcg_constant_i32(0), tcg_fpstatus);
break;
}
case 0x18: /* FRINTN */
case 0x19: /* FRINTM */
case 0x38: /* FRINTP */
@ -14011,7 +13894,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
}
if (is_scalar) {
tcg_res[1] = tcg_const_i64(0);
tcg_res[1] = tcg_constant_i64(0);
}
for (pass = 0; pass < 2; pass++) {
@ -14415,7 +14298,7 @@ static void disas_crypto_four_reg(DisasContext *s, uint32_t insn)
tcg_op2 = tcg_temp_new_i32();
tcg_op3 = tcg_temp_new_i32();
tcg_res = tcg_temp_new_i32();
tcg_zero = tcg_const_i32(0);
tcg_zero = tcg_constant_i32(0);
read_vec_element_i32(s, tcg_op1, rn, 3, MO_32);
read_vec_element_i32(s, tcg_op2, rm, 3, MO_32);
@ -14435,7 +14318,6 @@ static void disas_crypto_four_reg(DisasContext *s, uint32_t insn)
tcg_temp_free_i32(tcg_op2);
tcg_temp_free_i32(tcg_op3);
tcg_temp_free_i32(tcg_res);
tcg_temp_free_i32(tcg_zero);
}
}
@ -14943,22 +14825,19 @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
gen_helper_yield(cpu_env);
break;
case DISAS_WFI:
{
/* This is a special case because we don't want to just halt the CPU
* if trying to debug across a WFI.
/*
* This is a special case because we don't want to just halt
* the CPU if trying to debug across a WFI.
*/
TCGv_i32 tmp = tcg_const_i32(4);
gen_a64_set_pc_im(dc->base.pc_next);
gen_helper_wfi(cpu_env, tmp);
tcg_temp_free_i32(tmp);
/* The helper doesn't necessarily throw an exception, but we
gen_helper_wfi(cpu_env, tcg_constant_i32(4));
/*
* The helper doesn't necessarily throw an exception, but we
* must go back to the main loop to check for interrupts anyway.
*/
tcg_gen_exit_tb(NULL, 0);
break;
}
}
}
}

202
target/arm/translate-sve.c
View File

@ -282,13 +282,12 @@ static void do_predtest(DisasContext *s, int dofs, int gofs, int words)
{
TCGv_ptr dptr = tcg_temp_new_ptr();
TCGv_ptr gptr = tcg_temp_new_ptr();
TCGv_i32 t;
TCGv_i32 t = tcg_temp_new_i32();
tcg_gen_addi_ptr(dptr, cpu_env, dofs);
tcg_gen_addi_ptr(gptr, cpu_env, gofs);
t = tcg_const_i32(words);
gen_helper_sve_predtest(t, dptr, gptr, t);
gen_helper_sve_predtest(t, dptr, gptr, tcg_constant_i32(words));
tcg_temp_free_ptr(dptr);
tcg_temp_free_ptr(gptr);
@ -889,7 +888,7 @@ static bool do_vpz_ool(DisasContext *s, arg_rpr_esz *a,
return true;
}
desc = tcg_const_i32(simd_desc(vsz, vsz, 0));
desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
temp = tcg_temp_new_i64();
t_zn = tcg_temp_new_ptr();
t_pg = tcg_temp_new_ptr();
@ -899,7 +898,6 @@ static bool do_vpz_ool(DisasContext *s, arg_rpr_esz *a,
fn(temp, t_zn, t_pg, desc);
tcg_temp_free_ptr(t_zn);
tcg_temp_free_ptr(t_pg);
tcg_temp_free_i32(desc);
write_fp_dreg(s, a->rd, temp);
tcg_temp_free_i64(temp);
@ -1236,7 +1234,7 @@ static void do_index(DisasContext *s, int esz, int rd,
TCGv_i64 start, TCGv_i64 incr)
{
unsigned vsz = vec_full_reg_size(s);
TCGv_i32 desc = tcg_const_i32(simd_desc(vsz, vsz, 0));
TCGv_i32 desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
TCGv_ptr t_zd = tcg_temp_new_ptr();
tcg_gen_addi_ptr(t_zd, cpu_env, vec_full_reg_offset(s, rd));
@ -1260,17 +1258,14 @@ static void do_index(DisasContext *s, int esz, int rd,
tcg_temp_free_i32(i32);
}
tcg_temp_free_ptr(t_zd);
tcg_temp_free_i32(desc);
}
static bool trans_INDEX_ii(DisasContext *s, arg_INDEX_ii *a)
{
if (sve_access_check(s)) {
TCGv_i64 start = tcg_const_i64(a->imm1);
TCGv_i64 incr = tcg_const_i64(a->imm2);
TCGv_i64 start = tcg_constant_i64(a->imm1);
TCGv_i64 incr = tcg_constant_i64(a->imm2);
do_index(s, a->esz, a->rd, start, incr);
tcg_temp_free_i64(start);
tcg_temp_free_i64(incr);
}
return true;
}
@ -1278,10 +1273,9 @@ static bool trans_INDEX_ii(DisasContext *s, arg_INDEX_ii *a)
static bool trans_INDEX_ir(DisasContext *s, arg_INDEX_ir *a)
{
if (sve_access_check(s)) {
TCGv_i64 start = tcg_const_i64(a->imm);
TCGv_i64 start = tcg_constant_i64(a->imm);
TCGv_i64 incr = cpu_reg(s, a->rm);
do_index(s, a->esz, a->rd, start, incr);
tcg_temp_free_i64(start);
}
return true;
}
@ -1290,9 +1284,8 @@ static bool trans_INDEX_ri(DisasContext *s, arg_INDEX_ri *a)
{
if (sve_access_check(s)) {
TCGv_i64 start = cpu_reg(s, a->rn);
TCGv_i64 incr = tcg_const_i64(a->imm);
TCGv_i64 incr = tcg_constant_i64(a->imm);
do_index(s, a->esz, a->rd, start, incr);
tcg_temp_free_i64(incr);
}
return true;
}
@ -1884,9 +1877,9 @@ static bool do_pfirst_pnext(DisasContext *s, arg_rr_esz *a,
tcg_gen_addi_ptr(t_pd, cpu_env, pred_full_reg_offset(s, a->rd));
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->rn));
t = tcg_const_i32(desc);
t = tcg_temp_new_i32();
gen_fn(t, t_pd, t_pg, t);
gen_fn(t, t_pd, t_pg, tcg_constant_i32(desc));
tcg_temp_free_ptr(t_pd);
tcg_temp_free_ptr(t_pg);
@ -1993,7 +1986,7 @@ static void do_sat_addsub_vec(DisasContext *s, int esz, int rd, int rn,
nptr = tcg_temp_new_ptr();
tcg_gen_addi_ptr(dptr, cpu_env, vec_full_reg_offset(s, rd));
tcg_gen_addi_ptr(nptr, cpu_env, vec_full_reg_offset(s, rn));
desc = tcg_const_i32(simd_desc(vsz, vsz, 0));
desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
switch (esz) {
case MO_8:
@ -2062,7 +2055,6 @@ static void do_sat_addsub_vec(DisasContext *s, int esz, int rd, int rn,
tcg_temp_free_ptr(dptr);
tcg_temp_free_ptr(nptr);
tcg_temp_free_i32(desc);
}
static bool trans_CNT_r(DisasContext *s, arg_CNT_r *a)
@ -2107,9 +2099,7 @@ static bool trans_SINCDEC_r_32(DisasContext *s, arg_incdec_cnt *a)
tcg_gen_ext32s_i64(reg, reg);
}
} else {
TCGv_i64 t = tcg_const_i64(inc);
do_sat_addsub_32(reg, t, a->u, a->d);
tcg_temp_free_i64(t);
do_sat_addsub_32(reg, tcg_constant_i64(inc), a->u, a->d);
}
return true;
}
@ -2126,9 +2116,7 @@ static bool trans_SINCDEC_r_64(DisasContext *s, arg_incdec_cnt *a)
TCGv_i64 reg = cpu_reg(s, a->rd);
if (inc != 0) {
TCGv_i64 t = tcg_const_i64(inc);
do_sat_addsub_64(reg, t, a->u, a->d);
tcg_temp_free_i64(t);
do_sat_addsub_64(reg, tcg_constant_i64(inc), a->u, a->d);
}
return true;
}
@ -2145,11 +2133,10 @@ static bool trans_INCDEC_v(DisasContext *s, arg_incdec2_cnt *a)
if (inc != 0) {
if (sve_access_check(s)) {
TCGv_i64 t = tcg_const_i64(a->d ? -inc : inc);
tcg_gen_gvec_adds(a->esz, vec_full_reg_offset(s, a->rd),
vec_full_reg_offset(s, a->rn),
t, fullsz, fullsz);
tcg_temp_free_i64(t);
tcg_constant_i64(a->d ? -inc : inc),
fullsz, fullsz);
}
} else {
do_mov_z(s, a->rd, a->rn);
@ -2169,9 +2156,8 @@ static bool trans_SINCDEC_v(DisasContext *s, arg_incdec2_cnt *a)
if (inc != 0) {
if (sve_access_check(s)) {
TCGv_i64 t = tcg_const_i64(inc);
do_sat_addsub_vec(s, a->esz, a->rd, a->rn, t, a->u, a->d);
tcg_temp_free_i64(t);
do_sat_addsub_vec(s, a->esz, a->rd, a->rn,
tcg_constant_i64(inc), a->u, a->d);
}
} else {
do_mov_z(s, a->rd, a->rn);
@ -2244,7 +2230,7 @@ static void do_cpy_m(DisasContext *s, int esz, int rd, int rn, int pg,
gen_helper_sve_cpy_m_s, gen_helper_sve_cpy_m_d,
};
unsigned vsz = vec_full_reg_size(s);
TCGv_i32 desc = tcg_const_i32(simd_desc(vsz, vsz, 0));
TCGv_i32 desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
TCGv_ptr t_zd = tcg_temp_new_ptr();
TCGv_ptr t_zn = tcg_temp_new_ptr();
TCGv_ptr t_pg = tcg_temp_new_ptr();
@ -2258,7 +2244,6 @@ static void do_cpy_m(DisasContext *s, int esz, int rd, int rn, int pg,
tcg_temp_free_ptr(t_zd);
tcg_temp_free_ptr(t_zn);
tcg_temp_free_ptr(t_pg);
tcg_temp_free_i32(desc);
}
static bool trans_FCPY(DisasContext *s, arg_FCPY *a)
@ -2269,9 +2254,7 @@ static bool trans_FCPY(DisasContext *s, arg_FCPY *a)
if (sve_access_check(s)) {
/* Decode the VFP immediate. */
uint64_t imm = vfp_expand_imm(a->esz, a->imm);
TCGv_i64 t_imm = tcg_const_i64(imm);
do_cpy_m(s, a->esz, a->rd, a->rn, a->pg, t_imm);
tcg_temp_free_i64(t_imm);
do_cpy_m(s, a->esz, a->rd, a->rn, a->pg, tcg_constant_i64(imm));
}
return true;
}
@ -2282,9 +2265,7 @@ static bool trans_CPY_m_i(DisasContext *s, arg_rpri_esz *a)
return false;
}
if (sve_access_check(s)) {
TCGv_i64 t_imm = tcg_const_i64(a->imm);
do_cpy_m(s, a->esz, a->rd, a->rn, a->pg, t_imm);
tcg_temp_free_i64(t_imm);
do_cpy_m(s, a->esz, a->rd, a->rn, a->pg, tcg_constant_i64(a->imm));
}
return true;
}
@ -2301,11 +2282,10 @@ static bool trans_CPY_z_i(DisasContext *s, arg_CPY_z_i *a)
}
if (sve_access_check(s)) {
unsigned vsz = vec_full_reg_size(s);
TCGv_i64 t_imm = tcg_const_i64(a->imm);
tcg_gen_gvec_2i_ool(vec_full_reg_offset(s, a->rd),
pred_full_reg_offset(s, a->pg),
t_imm, vsz, vsz, 0, fns[a->esz]);
tcg_temp_free_i64(t_imm);
tcg_constant_i64(a->imm),
vsz, vsz, 0, fns[a->esz]);
}
return true;
}
@ -2406,7 +2386,7 @@ static void do_insr_i64(DisasContext *s, arg_rrr_esz *a, TCGv_i64 val)
gen_helper_sve_insr_s, gen_helper_sve_insr_d,
};
unsigned vsz = vec_full_reg_size(s);
TCGv_i32 desc = tcg_const_i32(simd_desc(vsz, vsz, 0));
TCGv_i32 desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
TCGv_ptr t_zd = tcg_temp_new_ptr();
TCGv_ptr t_zn = tcg_temp_new_ptr();
@ -2417,7 +2397,6 @@ static void do_insr_i64(DisasContext *s, arg_rrr_esz *a, TCGv_i64 val)
tcg_temp_free_ptr(t_zd);
tcg_temp_free_ptr(t_zn);
tcg_temp_free_i32(desc);
}
static bool trans_INSR_f(DisasContext *s, arg_rrr_esz *a)
@ -2536,7 +2515,6 @@ static bool do_perm_pred3(DisasContext *s, arg_rrr_esz *a, bool high_odd,
TCGv_ptr t_d = tcg_temp_new_ptr();
TCGv_ptr t_n = tcg_temp_new_ptr();
TCGv_ptr t_m = tcg_temp_new_ptr();
TCGv_i32 t_desc;
uint32_t desc = 0;
desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz);
@ -2546,14 +2524,12 @@ static bool do_perm_pred3(DisasContext *s, arg_rrr_esz *a, bool high_odd,
tcg_gen_addi_ptr(t_d, cpu_env, pred_full_reg_offset(s, a->rd));
tcg_gen_addi_ptr(t_n, cpu_env, pred_full_reg_offset(s, a->rn));
tcg_gen_addi_ptr(t_m, cpu_env, pred_full_reg_offset(s, a->rm));
t_desc = tcg_const_i32(desc);
fn(t_d, t_n, t_m, t_desc);
fn(t_d, t_n, t_m, tcg_constant_i32(desc));
tcg_temp_free_ptr(t_d);
tcg_temp_free_ptr(t_n);
tcg_temp_free_ptr(t_m);
tcg_temp_free_i32(t_desc);
return true;
}
@ -2567,7 +2543,6 @@ static bool do_perm_pred2(DisasContext *s, arg_rr_esz *a, bool high_odd,
unsigned vsz = pred_full_reg_size(s);
TCGv_ptr t_d = tcg_temp_new_ptr();
TCGv_ptr t_n = tcg_temp_new_ptr();
TCGv_i32 t_desc;
uint32_t desc = 0;
tcg_gen_addi_ptr(t_d, cpu_env, pred_full_reg_offset(s, a->rd));
@ -2576,11 +2551,9 @@ static bool do_perm_pred2(DisasContext *s, arg_rr_esz *a, bool high_odd,
desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz);
desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz);
desc = FIELD_DP32(desc, PREDDESC, DATA, high_odd);
t_desc = tcg_const_i32(desc);
fn(t_d, t_n, t_desc);
fn(t_d, t_n, tcg_constant_i32(desc));
tcg_temp_free_i32(t_desc);
tcg_temp_free_ptr(t_d);
tcg_temp_free_ptr(t_n);
return true;
@ -2782,18 +2755,15 @@ static void find_last_active(DisasContext *s, TCGv_i32 ret, int esz, int pg)
* round up, as we do elsewhere, because we need the exact size.
*/
TCGv_ptr t_p = tcg_temp_new_ptr();
TCGv_i32 t_desc;
unsigned desc = 0;
desc = FIELD_DP32(desc, PREDDESC, OPRSZ, pred_full_reg_size(s));
desc = FIELD_DP32(desc, PREDDESC, ESZ, esz);
tcg_gen_addi_ptr(t_p, cpu_env, pred_full_reg_offset(s, pg));
t_desc = tcg_const_i32(desc);
gen_helper_sve_last_active_element(ret, t_p, t_desc);
gen_helper_sve_last_active_element(ret, t_p, tcg_constant_i32(desc));
tcg_temp_free_i32(t_desc);
tcg_temp_free_ptr(t_p);
}
@ -2808,11 +2778,9 @@ static void incr_last_active(DisasContext *s, TCGv_i32 last, int esz)
if (is_power_of_2(vsz)) {
tcg_gen_andi_i32(last, last, vsz - 1);
} else {
TCGv_i32 max = tcg_const_i32(vsz);
TCGv_i32 zero = tcg_const_i32(0);
TCGv_i32 max = tcg_constant_i32(vsz);
TCGv_i32 zero = tcg_constant_i32(0);
tcg_gen_movcond_i32(TCG_COND_GEU, last, last, max, zero, last);
tcg_temp_free_i32(max);
tcg_temp_free_i32(zero);
}
}
@ -2824,11 +2792,9 @@ static void wrap_last_active(DisasContext *s, TCGv_i32 last, int esz)
if (is_power_of_2(vsz)) {
tcg_gen_andi_i32(last, last, vsz - 1);
} else {
TCGv_i32 max = tcg_const_i32(vsz - (1 << esz));
TCGv_i32 zero = tcg_const_i32(0);
TCGv_i32 max = tcg_constant_i32(vsz - (1 << esz));
TCGv_i32 zero = tcg_constant_i32(0);
tcg_gen_movcond_i32(TCG_COND_LT, last, last, zero, max, last);
tcg_temp_free_i32(max);
tcg_temp_free_i32(zero);
}
}
@ -2945,7 +2911,7 @@ static void do_clast_scalar(DisasContext *s, int esz, int pg, int rm,
bool before, TCGv_i64 reg_val)
{
TCGv_i32 last = tcg_temp_new_i32();
TCGv_i64 ele, cmp, zero;
TCGv_i64 ele, cmp;
find_last_active(s, last, esz, pg);
@ -2965,10 +2931,9 @@ static void do_clast_scalar(DisasContext *s, int esz, int pg, int rm,
ele = load_last_active(s, last, rm, esz);
tcg_temp_free_i32(last);
zero = tcg_const_i64(0);
tcg_gen_movcond_i64(TCG_COND_GE, reg_val, cmp, zero, ele, reg_val);
tcg_gen_movcond_i64(TCG_COND_GE, reg_val, cmp, tcg_constant_i64(0),
ele, reg_val);
tcg_temp_free_i64(zero);
tcg_temp_free_i64(cmp);
tcg_temp_free_i64(ele);
}
@ -3196,7 +3161,7 @@ static bool do_ppzz_flags(DisasContext *s, arg_rprr_esz *a,
}
vsz = vec_full_reg_size(s);
t = tcg_const_i32(simd_desc(vsz, vsz, 0));
t = tcg_temp_new_i32();
pd = tcg_temp_new_ptr();
zn = tcg_temp_new_ptr();
zm = tcg_temp_new_ptr();
@ -3207,7 +3172,7 @@ static bool do_ppzz_flags(DisasContext *s, arg_rprr_esz *a,
tcg_gen_addi_ptr(zm, cpu_env, vec_full_reg_offset(s, a->rm));
tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg));
gen_fn(t, pd, zn, zm, pg, t);
gen_fn(t, pd, zn, zm, pg, tcg_constant_i32(simd_desc(vsz, vsz, 0)));
tcg_temp_free_ptr(pd);
tcg_temp_free_ptr(zn);
@ -3281,7 +3246,7 @@ static bool do_ppzi_flags(DisasContext *s, arg_rpri_esz *a,
}
vsz = vec_full_reg_size(s);
t = tcg_const_i32(simd_desc(vsz, vsz, a->imm));
t = tcg_temp_new_i32();
pd = tcg_temp_new_ptr();
zn = tcg_temp_new_ptr();
pg = tcg_temp_new_ptr();
@ -3290,7 +3255,7 @@ static bool do_ppzi_flags(DisasContext *s, arg_rpri_esz *a,
tcg_gen_addi_ptr(zn, cpu_env, vec_full_reg_offset(s, a->rn));
tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg));
gen_fn(t, pd, zn, pg, t);
gen_fn(t, pd, zn, pg, tcg_constant_i32(simd_desc(vsz, vsz, a->imm)));
tcg_temp_free_ptr(pd);
tcg_temp_free_ptr(zn);
@ -3343,7 +3308,7 @@ static bool do_brk3(DisasContext *s, arg_rprr_s *a,
TCGv_ptr n = tcg_temp_new_ptr();
TCGv_ptr m = tcg_temp_new_ptr();
TCGv_ptr g = tcg_temp_new_ptr();
TCGv_i32 t = tcg_const_i32(FIELD_DP32(0, PREDDESC, OPRSZ, vsz));
TCGv_i32 desc = tcg_constant_i32(FIELD_DP32(0, PREDDESC, OPRSZ, vsz));
tcg_gen_addi_ptr(d, cpu_env, pred_full_reg_offset(s, a->rd));
tcg_gen_addi_ptr(n, cpu_env, pred_full_reg_offset(s, a->rn));
@ -3351,16 +3316,17 @@ static bool do_brk3(DisasContext *s, arg_rprr_s *a,
tcg_gen_addi_ptr(g, cpu_env, pred_full_reg_offset(s, a->pg));
if (a->s) {
fn_s(t, d, n, m, g, t);
TCGv_i32 t = tcg_temp_new_i32();
fn_s(t, d, n, m, g, desc);
do_pred_flags(t);
tcg_temp_free_i32(t);
} else {
fn(d, n, m, g, t);
fn(d, n, m, g, desc);
}
tcg_temp_free_ptr(d);
tcg_temp_free_ptr(n);
tcg_temp_free_ptr(m);
tcg_temp_free_ptr(g);
tcg_temp_free_i32(t);
return true;
}
@ -3377,22 +3343,23 @@ static bool do_brk2(DisasContext *s, arg_rpr_s *a,
TCGv_ptr d = tcg_temp_new_ptr();
TCGv_ptr n = tcg_temp_new_ptr();
TCGv_ptr g = tcg_temp_new_ptr();
TCGv_i32 t = tcg_const_i32(FIELD_DP32(0, PREDDESC, OPRSZ, vsz));
TCGv_i32 desc = tcg_constant_i32(FIELD_DP32(0, PREDDESC, OPRSZ, vsz));
tcg_gen_addi_ptr(d, cpu_env, pred_full_reg_offset(s, a->rd));
tcg_gen_addi_ptr(n, cpu_env, pred_full_reg_offset(s, a->rn));
tcg_gen_addi_ptr(g, cpu_env, pred_full_reg_offset(s, a->pg));
if (a->s) {
fn_s(t, d, n, g, t);
TCGv_i32 t = tcg_temp_new_i32();
fn_s(t, d, n, g, desc);
do_pred_flags(t);
tcg_temp_free_i32(t);
} else {
fn(d, n, g, t);
fn(d, n, g, desc);
}
tcg_temp_free_ptr(d);
tcg_temp_free_ptr(n);
tcg_temp_free_ptr(g);
tcg_temp_free_i32(t);
return true;
}
@ -3461,19 +3428,16 @@ static void do_cntp(DisasContext *s, TCGv_i64 val, int esz, int pn, int pg)
TCGv_ptr t_pn = tcg_temp_new_ptr();
TCGv_ptr t_pg = tcg_temp_new_ptr();
unsigned desc = 0;
TCGv_i32 t_desc;
desc = FIELD_DP32(desc, PREDDESC, OPRSZ, psz);
desc = FIELD_DP32(desc, PREDDESC, ESZ, esz);
tcg_gen_addi_ptr(t_pn, cpu_env, pred_full_reg_offset(s, pn));
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg));
t_desc = tcg_const_i32(desc);
gen_helper_sve_cntp(val, t_pn, t_pg, t_desc);
gen_helper_sve_cntp(val, t_pn, t_pg, tcg_constant_i32(desc));
tcg_temp_free_ptr(t_pn);
tcg_temp_free_ptr(t_pg);
tcg_temp_free_i32(t_desc);
}
}
@ -3588,7 +3552,7 @@ static bool trans_CTERM(DisasContext *s, arg_CTERM *a)
static bool trans_WHILE(DisasContext *s, arg_WHILE *a)
{
TCGv_i64 op0, op1, t0, t1, tmax;
TCGv_i32 t2, t3;
TCGv_i32 t2;
TCGv_ptr ptr;
unsigned vsz = vec_full_reg_size(s);
unsigned desc = 0;
@ -3644,7 +3608,7 @@ static bool trans_WHILE(DisasContext *s, arg_WHILE *a)
}
}
tmax = tcg_const_i64(vsz >> a->esz);
tmax = tcg_constant_i64(vsz >> a->esz);
if (eq) {
/* Equality means one more iteration. */
tcg_gen_addi_i64(t0, t0, 1);
@ -3664,7 +3628,6 @@ static bool trans_WHILE(DisasContext *s, arg_WHILE *a)
/* Bound to the maximum. */
tcg_gen_umin_i64(t0, t0, tmax);
tcg_temp_free_i64(tmax);
/* Set the count to zero if the condition is false. */
tcg_gen_movi_i64(t1, 0);
@ -3681,28 +3644,26 @@ static bool trans_WHILE(DisasContext *s, arg_WHILE *a)
desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz / 8);
desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz);
t3 = tcg_const_i32(desc);
ptr = tcg_temp_new_ptr();
tcg_gen_addi_ptr(ptr, cpu_env, pred_full_reg_offset(s, a->rd));
if (a->lt) {
gen_helper_sve_whilel(t2, ptr, t2, t3);
gen_helper_sve_whilel(t2, ptr, t2, tcg_constant_i32(desc));
} else {
gen_helper_sve_whileg(t2, ptr, t2, t3);
gen_helper_sve_whileg(t2, ptr, t2, tcg_constant_i32(desc));
}
do_pred_flags(t2);
tcg_temp_free_ptr(ptr);
tcg_temp_free_i32(t2);
tcg_temp_free_i32(t3);
return true;
}
static bool trans_WHILE_ptr(DisasContext *s, arg_WHILE_ptr *a)
{
TCGv_i64 op0, op1, diff, t1, tmax;
TCGv_i32 t2, t3;
TCGv_i32 t2;
TCGv_ptr ptr;
unsigned vsz = vec_full_reg_size(s);
unsigned desc = 0;
@ -3717,7 +3678,7 @@ static bool trans_WHILE_ptr(DisasContext *s, arg_WHILE_ptr *a)
op0 = read_cpu_reg(s, a->rn, 1);
op1 = read_cpu_reg(s, a->rm, 1);
tmax = tcg_const_i64(vsz);
tmax = tcg_constant_i64(vsz);
diff = tcg_temp_new_i64();
if (a->rw) {
@ -3743,7 +3704,6 @@ static bool trans_WHILE_ptr(DisasContext *s, arg_WHILE_ptr *a)
/* Bound to the maximum. */
tcg_gen_umin_i64(diff, diff, tmax);
tcg_temp_free_i64(tmax);
/* Since we're bounded, pass as a 32-bit type. */
t2 = tcg_temp_new_i32();
@ -3752,17 +3712,15 @@ static bool trans_WHILE_ptr(DisasContext *s, arg_WHILE_ptr *a)
desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz / 8);
desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz);
t3 = tcg_const_i32(desc);
ptr = tcg_temp_new_ptr();
tcg_gen_addi_ptr(ptr, cpu_env, pred_full_reg_offset(s, a->rd));
gen_helper_sve_whilel(t2, ptr, t2, t3);
gen_helper_sve_whilel(t2, ptr, t2, tcg_constant_i32(desc));
do_pred_flags(t2);
tcg_temp_free_ptr(ptr);
tcg_temp_free_i32(t2);
tcg_temp_free_i32(t3);
return true;
}
@ -3856,11 +3814,9 @@ static bool trans_SUBR_zzi(DisasContext *s, arg_rri_esz *a)
}
if (sve_access_check(s)) {
unsigned vsz = vec_full_reg_size(s);
TCGv_i64 c = tcg_const_i64(a->imm);
tcg_gen_gvec_2s(vec_full_reg_offset(s, a->rd),
vec_full_reg_offset(s, a->rn),
vsz, vsz, c, &op[a->esz]);
tcg_temp_free_i64(c);
vsz, vsz, tcg_constant_i64(a->imm), &op[a->esz]);
}
return true;
}
@ -3881,9 +3837,8 @@ static bool do_zzi_sat(DisasContext *s, arg_rri_esz *a, bool u, bool d)
return false;
}
if (sve_access_check(s)) {
TCGv_i64 val = tcg_const_i64(a->imm);
do_sat_addsub_vec(s, a->esz, a->rd, a->rn, val, u, d);
tcg_temp_free_i64(val);
do_sat_addsub_vec(s, a->esz, a->rd, a->rn,
tcg_constant_i64(a->imm), u, d);
}
return true;
}
@ -3912,12 +3867,9 @@ static bool do_zzi_ool(DisasContext *s, arg_rri_esz *a, gen_helper_gvec_2i *fn)
{
if (sve_access_check(s)) {
unsigned vsz = vec_full_reg_size(s);
TCGv_i64 c = tcg_const_i64(a->imm);
tcg_gen_gvec_2i_ool(vec_full_reg_offset(s, a->rd),
vec_full_reg_offset(s, a->rn),
c, vsz, vsz, 0, fn);
tcg_temp_free_i64(c);
tcg_constant_i64(a->imm), vsz, vsz, 0, fn);
}
return true;
}
@ -4221,7 +4173,7 @@ static void do_reduce(DisasContext *s, arg_rpr_esz *a,
{
unsigned vsz = vec_full_reg_size(s);
unsigned p2vsz = pow2ceil(vsz);
TCGv_i32 t_desc = tcg_const_i32(simd_desc(vsz, vsz, p2vsz));
TCGv_i32 t_desc = tcg_constant_i32(simd_desc(vsz, vsz, p2vsz));
TCGv_ptr t_zn, t_pg, status;
TCGv_i64 temp;
@ -4237,7 +4189,6 @@ static void do_reduce(DisasContext *s, arg_rpr_esz *a,
tcg_temp_free_ptr(t_zn);
tcg_temp_free_ptr(t_pg);
tcg_temp_free_ptr(status);
tcg_temp_free_i32(t_desc);
write_fp_dreg(s, a->rd, temp);
tcg_temp_free_i64(temp);
@ -4414,11 +4365,10 @@ static bool trans_FADDA(DisasContext *s, arg_rprr_esz *a)
tcg_gen_addi_ptr(t_rm, cpu_env, vec_full_reg_offset(s, a->rm));
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->pg));
t_fpst = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
t_desc = tcg_const_i32(simd_desc(vsz, vsz, 0));
t_desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
fns[a->esz - 1](t_val, t_val, t_rm, t_pg, t_fpst, t_desc);
tcg_temp_free_i32(t_desc);
tcg_temp_free_ptr(t_fpst);
tcg_temp_free_ptr(t_pg);
tcg_temp_free_ptr(t_rm);
@ -4535,10 +4485,9 @@ static void do_fp_scalar(DisasContext *s, int zd, int zn, int pg, bool is_fp16,
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg));
status = fpstatus_ptr(is_fp16 ? FPST_FPCR_F16 : FPST_FPCR);
desc = tcg_const_i32(simd_desc(vsz, vsz, 0));
desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
fn(t_zd, t_zn, t_pg, scalar, status, desc);
tcg_temp_free_i32(desc);
tcg_temp_free_ptr(status);
tcg_temp_free_ptr(t_pg);
tcg_temp_free_ptr(t_zn);
@ -4548,9 +4497,8 @@ static void do_fp_scalar(DisasContext *s, int zd, int zn, int pg, bool is_fp16,
static void do_fp_imm(DisasContext *s, arg_rpri_esz *a, uint64_t imm,
gen_helper_sve_fp2scalar *fn)
{
TCGv_i64 temp = tcg_const_i64(imm);
do_fp_scalar(s, a->rd, a->rn, a->pg, a->esz == MO_16, temp, fn);
tcg_temp_free_i64(temp);
do_fp_scalar(s, a->rd, a->rn, a->pg, a->esz == MO_16,
tcg_constant_i64(imm), fn);
}
#define DO_FP_IMM(NAME, name, const0, const1) \
@ -5297,7 +5245,6 @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
{
unsigned vsz = vec_full_reg_size(s);
TCGv_ptr t_pg;
TCGv_i32 t_desc;
int desc = 0;
/*
@ -5319,14 +5266,12 @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
}
desc = simd_desc(vsz, vsz, zt | desc);
t_desc = tcg_const_i32(desc);
t_pg = tcg_temp_new_ptr();
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg));
fn(cpu_env, t_pg, addr, t_desc);
fn(cpu_env, t_pg, addr, tcg_constant_i32(desc));
tcg_temp_free_ptr(t_pg);
tcg_temp_free_i32(t_desc);
}
/* Indexed by [mte][be][dtype][nreg] */
@ -6069,7 +6014,6 @@ static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm,
TCGv_ptr t_zm = tcg_temp_new_ptr();
TCGv_ptr t_pg = tcg_temp_new_ptr();
TCGv_ptr t_zt = tcg_temp_new_ptr();
TCGv_i32 t_desc;
int desc = 0;
if (s->mte_active[0]) {
@ -6081,17 +6025,15 @@ static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm,
desc <<= SVE_MTEDESC_SHIFT;
}
desc = simd_desc(vsz, vsz, desc | scale);
t_desc = tcg_const_i32(desc);
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg));
tcg_gen_addi_ptr(t_zm, cpu_env, vec_full_reg_offset(s, zm));
tcg_gen_addi_ptr(t_zt, cpu_env, vec_full_reg_offset(s, zt));
fn(cpu_env, t_zt, t_pg, t_zm, scalar, t_desc);
fn(cpu_env, t_zt, t_pg, t_zm, scalar, tcg_constant_i32(desc));
tcg_temp_free_ptr(t_zt);
tcg_temp_free_ptr(t_zm);
tcg_temp_free_ptr(t_pg);
tcg_temp_free_i32(t_desc);
}
/* Indexed by [mte][be][ff][xs][u][msz]. */
@ -6452,7 +6394,6 @@ static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_zpiz *a)
gen_helper_gvec_mem_scatter *fn = NULL;
bool be = s->be_data == MO_BE;
bool mte = s->mte_active[0];
TCGv_i64 imm;
if (a->esz < a->msz || (a->esz == a->msz && !a->u)) {
return false;
@ -6474,9 +6415,8 @@ static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_zpiz *a)
/* Treat LD1_zpiz (zn[x] + imm) the same way as LD1_zprz (rn + zm[x])
* by loading the immediate into the scalar parameter.
*/
imm = tcg_const_i64(a->imm << a->msz);
do_mem_zpz(s, a->rd, a->pg, a->rn, 0, imm, a->msz, false, fn);
tcg_temp_free_i64(imm);
do_mem_zpz(s, a->rd, a->pg, a->rn, 0,
tcg_constant_i64(a->imm << a->msz), a->msz, false, fn);
return true;
}
@ -6635,7 +6575,6 @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a)
gen_helper_gvec_mem_scatter *fn = NULL;
bool be = s->be_data == MO_BE;
bool mte = s->mte_active[0];
TCGv_i64 imm;
if (a->esz < a->msz) {
return false;
@ -6657,9 +6596,8 @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a)
/* Treat ST1_zpiz (zn[x] + imm) the same way as ST1_zprz (rn + zm[x])
* by loading the immediate into the scalar parameter.
*/
imm = tcg_const_i64(a->imm << a->msz);
do_mem_zpz(s, a->rd, a->pg, a->rn, 0, imm, a->msz, true, fn);
tcg_temp_free_i64(imm);
do_mem_zpz(s, a->rd, a->pg, a->rn, 0,
tcg_constant_i64(a->imm << a->msz), a->msz, true, fn);
return true;
}

244
target/arm/translate.c
View File

@ -346,9 +346,7 @@ static void store_sp_checked(DisasContext *s, TCGv_i32 var)
void gen_set_cpsr(TCGv_i32 var, uint32_t mask)
{
TCGv_i32 tmp_mask = tcg_const_i32(mask);
gen_helper_cpsr_write(cpu_env, var, tmp_mask);
tcg_temp_free_i32(tmp_mask);
gen_helper_cpsr_write(cpu_env, var, tcg_constant_i32(mask));
}
static void gen_rebuild_hflags(DisasContext *s, bool new_el)
@ -373,11 +371,8 @@ static void gen_rebuild_hflags(DisasContext *s, bool new_el)
static void gen_exception_internal(int excp)
{
TCGv_i32 tcg_excp = tcg_const_i32(excp);
assert(excp_is_internal(excp));
gen_helper_exception_internal(cpu_env, tcg_excp);
tcg_temp_free_i32(tcg_excp);
gen_helper_exception_internal(cpu_env, tcg_constant_i32(excp));
}
static void gen_singlestep_exception(DisasContext *s)
@ -1078,12 +1073,8 @@ static inline void gen_smc(DisasContext *s)
/* As with HVC, we may take an exception either before or after
* the insn executes.
*/
TCGv_i32 tmp;
gen_set_pc_im(s, s->pc_curr);
tmp = tcg_const_i32(syn_aa32_smc());
gen_helper_pre_smc(cpu_env, tmp);
tcg_temp_free_i32(tmp);
gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa32_smc()));
gen_set_pc_im(s, s->base.pc_next);
s->base.is_jmp = DISAS_SMC;
}
@ -1111,13 +1102,9 @@ void gen_exception_insn(DisasContext *s, uint64_t pc, int excp,
static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
{
TCGv_i32 tcg_syn;
gen_set_condexec(s);
gen_set_pc_im(s, s->pc_curr);
tcg_syn = tcg_const_i32(syn);
gen_helper_exception_bkpt_insn(cpu_env, tcg_syn);
tcg_temp_free_i32(tcg_syn);
gen_helper_exception_bkpt_insn(cpu_env, tcg_constant_i32(syn));
s->base.is_jmp = DISAS_NORETURN;
}
@ -1131,16 +1118,11 @@ void unallocated_encoding(DisasContext *s)
static void gen_exception_el(DisasContext *s, int excp, uint32_t syn,
TCGv_i32 tcg_el)
{
TCGv_i32 tcg_excp;
TCGv_i32 tcg_syn;
gen_set_condexec(s);
gen_set_pc_im(s, s->pc_curr);
tcg_excp = tcg_const_i32(excp);
tcg_syn = tcg_const_i32(syn);
gen_helper_exception_with_syndrome(cpu_env, tcg_excp, tcg_syn, tcg_el);
tcg_temp_free_i32(tcg_syn);
tcg_temp_free_i32(tcg_excp);
gen_helper_exception_with_syndrome(cpu_env,
tcg_constant_i32(excp),
tcg_constant_i32(syn), tcg_el);
s->base.is_jmp = DISAS_NORETURN;
}
@ -1863,24 +1845,21 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn)
gen_op_iwmmxt_movq_M0_wRn(wrd);
switch ((insn >> 6) & 3) {
case 0:
tmp2 = tcg_const_i32(0xff);
tmp3 = tcg_const_i32((insn & 7) << 3);
tmp2 = tcg_constant_i32(0xff);
tmp3 = tcg_constant_i32((insn & 7) << 3);
break;
case 1:
tmp2 = tcg_const_i32(0xffff);
tmp3 = tcg_const_i32((insn & 3) << 4);
tmp2 = tcg_constant_i32(0xffff);
tmp3 = tcg_constant_i32((insn & 3) << 4);
break;
case 2:
tmp2 = tcg_const_i32(0xffffffff);
tmp3 = tcg_const_i32((insn & 1) << 5);
tmp2 = tcg_constant_i32(0xffffffff);
tmp3 = tcg_constant_i32((insn & 1) << 5);
break;
default:
tmp2 = NULL;
tmp3 = NULL;
g_assert_not_reached();
}
gen_helper_iwmmxt_insr(cpu_M0, cpu_M0, tmp, tmp2, tmp3);
tcg_temp_free_i32(tmp3);
tcg_temp_free_i32(tmp2);
tcg_temp_free_i32(tmp);
gen_op_iwmmxt_movq_wRn_M0(wrd);
gen_op_iwmmxt_set_mup();
@ -2336,10 +2315,9 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn)
rd0 = (insn >> 16) & 0xf;
rd1 = (insn >> 0) & 0xf;
gen_op_iwmmxt_movq_M0_wRn(rd0);
tmp = tcg_const_i32((insn >> 20) & 3);
iwmmxt_load_reg(cpu_V1, rd1);
gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp);
tcg_temp_free_i32(tmp);
gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1,
tcg_constant_i32((insn >> 20) & 3));
gen_op_iwmmxt_movq_wRn_M0(wrd);
gen_op_iwmmxt_set_mup();
break;
@ -2393,9 +2371,8 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn)
wrd = (insn >> 12) & 0xf;
rd0 = (insn >> 16) & 0xf;
gen_op_iwmmxt_movq_M0_wRn(rd0);
tmp = tcg_const_i32(((insn >> 16) & 0xf0) | (insn & 0x0f));
tmp = tcg_constant_i32(((insn >> 16) & 0xf0) | (insn & 0x0f));
gen_helper_iwmmxt_shufh(cpu_M0, cpu_env, cpu_M0, tmp);
tcg_temp_free_i32(tmp);
gen_op_iwmmxt_movq_wRn_M0(wrd);
gen_op_iwmmxt_set_mup();
gen_op_iwmmxt_set_cup();
@ -2868,7 +2845,7 @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn,
tcg_gen_sextract_i32(tcg_el, tcg_el, ctz32(SCR_EEL2), 1);
tcg_gen_addi_i32(tcg_el, tcg_el, 3);
} else {
tcg_el = tcg_const_i32(3);
tcg_el = tcg_constant_i32(3);
}
gen_exception_el(s, EXCP_UDEF, syn_uncategorized(), tcg_el);
@ -2903,7 +2880,7 @@ undef:
static void gen_msr_banked(DisasContext *s, int r, int sysm, int rn)
{
TCGv_i32 tcg_reg, tcg_tgtmode, tcg_regno;
TCGv_i32 tcg_reg;
int tgtmode = 0, regno = 0;
if (!msr_banked_access_decode(s, r, sysm, rn, &tgtmode, &regno)) {
@ -2914,18 +2891,16 @@ static void gen_msr_banked(DisasContext *s, int r, int sysm, int rn)
gen_set_condexec(s);
gen_set_pc_im(s, s->pc_curr);
tcg_reg = load_reg(s, rn);
tcg_tgtmode = tcg_const_i32(tgtmode);
tcg_regno = tcg_const_i32(regno);
gen_helper_msr_banked(cpu_env, tcg_reg, tcg_tgtmode, tcg_regno);
tcg_temp_free_i32(tcg_tgtmode);
tcg_temp_free_i32(tcg_regno);
gen_helper_msr_banked(cpu_env, tcg_reg,
tcg_constant_i32(tgtmode),
tcg_constant_i32(regno));
tcg_temp_free_i32(tcg_reg);
s->base.is_jmp = DISAS_UPDATE_EXIT;
}
static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn)
{
TCGv_i32 tcg_reg, tcg_tgtmode, tcg_regno;
TCGv_i32 tcg_reg;
int tgtmode = 0, regno = 0;
if (!msr_banked_access_decode(s, r, sysm, rn, &tgtmode, &regno)) {
@ -2936,11 +2911,9 @@ static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn)
gen_set_condexec(s);
gen_set_pc_im(s, s->pc_curr);
tcg_reg = tcg_temp_new_i32();
tcg_tgtmode = tcg_const_i32(tgtmode);
tcg_regno = tcg_const_i32(regno);
gen_helper_mrs_banked(tcg_reg, cpu_env, tcg_tgtmode, tcg_regno);
tcg_temp_free_i32(tcg_tgtmode);
tcg_temp_free_i32(tcg_regno);
gen_helper_mrs_banked(tcg_reg, cpu_env,
tcg_constant_i32(tgtmode),
tcg_constant_i32(regno));
store_reg(s, rn, tcg_reg);
s->base.is_jmp = DISAS_UPDATE_EXIT;
}
@ -3023,9 +2996,8 @@ void gen_gvec_sqrdmlsh_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
} \
static void gen_##NAME##0_vec(unsigned vece, TCGv_vec d, TCGv_vec a) \
{ \
TCGv_vec zero = tcg_const_zeros_vec_matching(d); \
TCGv_vec zero = tcg_constant_vec_matching(d, vece, 0); \
tcg_gen_cmp_vec(COND, vece, d, a, zero); \
tcg_temp_free_vec(zero); \
} \
void gen_gvec_##NAME##0(unsigned vece, uint32_t d, uint32_t m, \
uint32_t opr_sz, uint32_t max_sz) \
@ -4015,8 +3987,8 @@ void gen_ushl_i32(TCGv_i32 dst, TCGv_i32 src, TCGv_i32 shift)
TCGv_i32 rval = tcg_temp_new_i32();
TCGv_i32 lsh = tcg_temp_new_i32();
TCGv_i32 rsh = tcg_temp_new_i32();
TCGv_i32 zero = tcg_const_i32(0);
TCGv_i32 max = tcg_const_i32(32);
TCGv_i32 zero = tcg_constant_i32(0);
TCGv_i32 max = tcg_constant_i32(32);
/*
* Rely on the TCG guarantee that out of range shifts produce
@ -4034,8 +4006,6 @@ void gen_ushl_i32(TCGv_i32 dst, TCGv_i32 src, TCGv_i32 shift)
tcg_temp_free_i32(rval);
tcg_temp_free_i32(lsh);
tcg_temp_free_i32(rsh);
tcg_temp_free_i32(zero);
tcg_temp_free_i32(max);
}
void gen_ushl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 shift)
@ -4044,8 +4014,8 @@ void gen_ushl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 shift)
TCGv_i64 rval = tcg_temp_new_i64();
TCGv_i64 lsh = tcg_temp_new_i64();
TCGv_i64 rsh = tcg_temp_new_i64();
TCGv_i64 zero = tcg_const_i64(0);
TCGv_i64 max = tcg_const_i64(64);
TCGv_i64 zero = tcg_constant_i64(0);
TCGv_i64 max = tcg_constant_i64(64);
/*
* Rely on the TCG guarantee that out of range shifts produce
@ -4063,8 +4033,6 @@ void gen_ushl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 shift)
tcg_temp_free_i64(rval);
tcg_temp_free_i64(lsh);
tcg_temp_free_i64(rsh);
tcg_temp_free_i64(zero);
tcg_temp_free_i64(max);
}
static void gen_ushl_vec(unsigned vece, TCGv_vec dst,
@ -4159,8 +4127,8 @@ void gen_sshl_i32(TCGv_i32 dst, TCGv_i32 src, TCGv_i32 shift)
TCGv_i32 rval = tcg_temp_new_i32();
TCGv_i32 lsh = tcg_temp_new_i32();
TCGv_i32 rsh = tcg_temp_new_i32();
TCGv_i32 zero = tcg_const_i32(0);
TCGv_i32 max = tcg_const_i32(31);
TCGv_i32 zero = tcg_constant_i32(0);
TCGv_i32 max = tcg_constant_i32(31);
/*
* Rely on the TCG guarantee that out of range shifts produce
@ -4179,8 +4147,6 @@ void gen_sshl_i32(TCGv_i32 dst, TCGv_i32 src, TCGv_i32 shift)
tcg_temp_free_i32(rval);
tcg_temp_free_i32(lsh);
tcg_temp_free_i32(rsh);
tcg_temp_free_i32(zero);
tcg_temp_free_i32(max);
}
void gen_sshl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 shift)
@ -4189,8 +4155,8 @@ void gen_sshl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 shift)
TCGv_i64 rval = tcg_temp_new_i64();
TCGv_i64 lsh = tcg_temp_new_i64();
TCGv_i64 rsh = tcg_temp_new_i64();
TCGv_i64 zero = tcg_const_i64(0);
TCGv_i64 max = tcg_const_i64(63);
TCGv_i64 zero = tcg_constant_i64(0);
TCGv_i64 max = tcg_constant_i64(63);
/*
* Rely on the TCG guarantee that out of range shifts produce
@ -4209,8 +4175,6 @@ void gen_sshl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 shift)
tcg_temp_free_i64(rval);
tcg_temp_free_i64(lsh);
tcg_temp_free_i64(rsh);
tcg_temp_free_i64(zero);
tcg_temp_free_i64(max);
}
static void gen_sshl_vec(unsigned vece, TCGv_vec dst,
@ -4725,8 +4689,6 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
* Note that on XScale all cp0..c13 registers do an access check
* call in order to handle c15_cpar.
*/
TCGv_ptr tmpptr;
TCGv_i32 tcg_syn, tcg_isread;
uint32_t syndrome;
/* Note that since we are an implementation which takes an
@ -4769,14 +4731,10 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
gen_set_condexec(s);
gen_set_pc_im(s, s->pc_curr);
tmpptr = tcg_const_ptr(ri);
tcg_syn = tcg_const_i32(syndrome);
tcg_isread = tcg_const_i32(isread);
gen_helper_access_check_cp_reg(cpu_env, tmpptr, tcg_syn,
tcg_isread);
tcg_temp_free_ptr(tmpptr);
tcg_temp_free_i32(tcg_syn);
tcg_temp_free_i32(tcg_isread);
gen_helper_access_check_cp_reg(cpu_env,
tcg_constant_ptr(ri),
tcg_constant_i32(syndrome),
tcg_constant_i32(isread));
} else if (ri->type & ARM_CP_RAISES_EXC) {
/*
* The readfn or writefn might raise an exception;
@ -4812,13 +4770,11 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
TCGv_i64 tmp64;
TCGv_i32 tmp;
if (ri->type & ARM_CP_CONST) {
tmp64 = tcg_const_i64(ri->resetvalue);
tmp64 = tcg_constant_i64(ri->resetvalue);
} else if (ri->readfn) {
TCGv_ptr tmpptr;
tmp64 = tcg_temp_new_i64();
tmpptr = tcg_const_ptr(ri);
gen_helper_get_cp_reg64(tmp64, cpu_env, tmpptr);
tcg_temp_free_ptr(tmpptr);
gen_helper_get_cp_reg64(tmp64, cpu_env,
tcg_constant_ptr(ri));
} else {
tmp64 = tcg_temp_new_i64();
tcg_gen_ld_i64(tmp64, cpu_env, ri->fieldoffset);
@ -4833,13 +4789,10 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
} else {
TCGv_i32 tmp;
if (ri->type & ARM_CP_CONST) {
tmp = tcg_const_i32(ri->resetvalue);
tmp = tcg_constant_i32(ri->resetvalue);
} else if (ri->readfn) {
TCGv_ptr tmpptr;
tmp = tcg_temp_new_i32();
tmpptr = tcg_const_ptr(ri);
gen_helper_get_cp_reg(tmp, cpu_env, tmpptr);
tcg_temp_free_ptr(tmpptr);
gen_helper_get_cp_reg(tmp, cpu_env, tcg_constant_ptr(ri));
} else {
tmp = load_cpu_offset(ri->fieldoffset);
}
@ -4869,24 +4822,18 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
tcg_temp_free_i32(tmplo);
tcg_temp_free_i32(tmphi);
if (ri->writefn) {
TCGv_ptr tmpptr = tcg_const_ptr(ri);
gen_helper_set_cp_reg64(cpu_env, tmpptr, tmp64);
tcg_temp_free_ptr(tmpptr);
gen_helper_set_cp_reg64(cpu_env, tcg_constant_ptr(ri),
tmp64);
} else {
tcg_gen_st_i64(tmp64, cpu_env, ri->fieldoffset);
}
tcg_temp_free_i64(tmp64);
} else {
TCGv_i32 tmp = load_reg(s, rt);
if (ri->writefn) {
TCGv_i32 tmp;
TCGv_ptr tmpptr;
tmp = load_reg(s, rt);
tmpptr = tcg_const_ptr(ri);
gen_helper_set_cp_reg(cpu_env, tmpptr, tmp);
tcg_temp_free_ptr(tmpptr);
gen_helper_set_cp_reg(cpu_env, tcg_constant_ptr(ri), tmp);
tcg_temp_free_i32(tmp);
} else {
TCGv_i32 tmp = load_reg(s, rt);
store_cpu_offset(tmp, ri->fieldoffset, 4);
}
}
@ -5190,12 +5137,10 @@ static void gen_srs(DisasContext *s,
}
addr = tcg_temp_new_i32();
tmp = tcg_const_i32(mode);
/* get_r13_banked() will raise an exception if called from System mode */
gen_set_condexec(s);
gen_set_pc_im(s, s->pc_curr);
gen_helper_get_r13_banked(addr, cpu_env, tmp);
tcg_temp_free_i32(tmp);
gen_helper_get_r13_banked(addr, cpu_env, tcg_constant_i32(mode));
switch (amode) {
case 0: /* DA */
offset = -4;
@ -5238,9 +5183,7 @@ static void gen_srs(DisasContext *s,
abort();
}
tcg_gen_addi_i32(addr, addr, offset);
tmp = tcg_const_i32(mode);
gen_helper_set_r13_banked(cpu_env, tmp, addr);
tcg_temp_free_i32(tmp);
gen_helper_set_r13_banked(cpu_env, tcg_constant_i32(mode), addr);
}
tcg_temp_free_i32(addr);
s->base.is_jmp = DISAS_UPDATE_EXIT;
@ -5552,18 +5495,16 @@ static bool op_s_rri_rot(DisasContext *s, arg_s_rri_rot *a,
void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32),
int logic_cc, StoreRegKind kind)
{
TCGv_i32 tmp1, tmp2;
TCGv_i32 tmp1;
uint32_t imm;
imm = ror32(a->imm, a->rot);
if (logic_cc && a->rot) {
tcg_gen_movi_i32(cpu_CF, imm >> 31);
}
tmp2 = tcg_const_i32(imm);
tmp1 = load_reg(s, a->rn);
gen(tmp1, tmp1, tmp2);
tcg_temp_free_i32(tmp2);
gen(tmp1, tmp1, tcg_constant_i32(imm));
if (logic_cc) {
gen_logic_CC(tmp1);
@ -5582,9 +5523,10 @@ static bool op_s_rxi_rot(DisasContext *s, arg_s_rri_rot *a,
if (logic_cc && a->rot) {
tcg_gen_movi_i32(cpu_CF, imm >> 31);
}
tmp = tcg_const_i32(imm);
gen(tmp, tmp);
tmp = tcg_temp_new_i32();
gen(tmp, tcg_constant_i32(imm));
if (logic_cc) {
gen_logic_CC(tmp);
}
@ -5710,14 +5652,11 @@ static bool trans_ADR(DisasContext *s, arg_ri *a)
static bool trans_MOVW(DisasContext *s, arg_MOVW *a)
{
TCGv_i32 tmp;
if (!ENABLE_ARCH_6T2) {
return false;
}
tmp = tcg_const_i32(a->imm);
store_reg(s, a->rd, tmp);
store_reg(s, a->rd, tcg_constant_i32(a->imm));
return true;
}
@ -6088,14 +6027,13 @@ static bool trans_UMAAL(DisasContext *s, arg_UMAAL *a)
t0 = load_reg(s, a->rm);
t1 = load_reg(s, a->rn);
tcg_gen_mulu2_i32(t0, t1, t0, t1);
zero = tcg_const_i32(0);
zero = tcg_constant_i32(0);
t2 = load_reg(s, a->ra);
tcg_gen_add2_i32(t0, t1, t0, t1, t2, zero);
tcg_temp_free_i32(t2);
t2 = load_reg(s, a->rd);
tcg_gen_add2_i32(t0, t1, t0, t1, t2, zero);
tcg_temp_free_i32(t2);
tcg_temp_free_i32(zero);
store_reg(s, a->ra, t0);
store_reg(s, a->rd, t1);
return true;
@ -6342,14 +6280,13 @@ static bool op_crc32(DisasContext *s, arg_rrr *a, bool c, MemOp sz)
default:
g_assert_not_reached();
}
t3 = tcg_const_i32(1 << sz);
t3 = tcg_constant_i32(1 << sz);
if (c) {
gen_helper_crc32c(t1, t1, t2, t3);
} else {
gen_helper_crc32(t1, t1, t2, t3);
}
tcg_temp_free_i32(t2);
tcg_temp_free_i32(t3);
store_reg(s, a->rd, t1);
return true;
}
@ -6432,8 +6369,8 @@ static bool trans_MRS_v7m(DisasContext *s, arg_MRS_v7m *a)
if (!arm_dc_feature(s, ARM_FEATURE_M)) {
return false;
}
tmp = tcg_const_i32(a->sysm);
gen_helper_v7m_mrs(tmp, cpu_env, tmp);
tmp = tcg_temp_new_i32();
gen_helper_v7m_mrs(tmp, cpu_env, tcg_constant_i32(a->sysm));
store_reg(s, a->rd, tmp);
return true;
}
@ -6445,10 +6382,9 @@ static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7m *a)
if (!arm_dc_feature(s, ARM_FEATURE_M)) {
return false;
}
addr = tcg_const_i32((a->mask << 10) | a->sysm);
addr = tcg_constant_i32((a->mask << 10) | a->sysm);
reg = load_reg(s, a->rn);
gen_helper_v7m_msr(cpu_env, addr, reg);
tcg_temp_free_i32(addr);
tcg_temp_free_i32(reg);
/* If we wrote to CONTROL, the EL might have changed */
gen_rebuild_hflags(s, true);
@ -6660,8 +6596,8 @@ static bool trans_TT(DisasContext *s, arg_TT *a)
}
addr = load_reg(s, a->rn);
tmp = tcg_const_i32((a->A << 1) | a->T);
gen_helper_v7m_tt(tmp, cpu_env, addr, tmp);
tmp = tcg_temp_new_i32();
gen_helper_v7m_tt(tmp, cpu_env, addr, tcg_constant_i32((a->A << 1) | a->T));
tcg_temp_free_i32(addr);
store_reg(s, a->rd, tmp);
return true;
@ -7628,7 +7564,7 @@ static bool trans_PKH(DisasContext *s, arg_PKH *a)
static bool op_sat(DisasContext *s, arg_sat *a,
void (*gen)(TCGv_i32, TCGv_env, TCGv_i32, TCGv_i32))
{
TCGv_i32 tmp, satimm;
TCGv_i32 tmp;
int shift = a->imm;
if (!ENABLE_ARCH_6) {
@ -7642,9 +7578,7 @@ static bool op_sat(DisasContext *s, arg_sat *a,
tcg_gen_shli_i32(tmp, tmp, shift);
}
satimm = tcg_const_i32(a->satimm);
gen(tmp, cpu_env, tmp, satimm);
tcg_temp_free_i32(satimm);
gen(tmp, cpu_env, tmp, tcg_constant_i32(a->satimm));
store_reg(s, a->rd, tmp);
return true;
@ -7979,9 +7913,7 @@ static bool op_smmla(DisasContext *s, arg_rrrr *a, bool round, bool sub)
* a non-zero multiplicand lowpart, and the correct result
* lowpart for rounding.
*/
TCGv_i32 zero = tcg_const_i32(0);
tcg_gen_sub2_i32(t2, t1, zero, t3, t2, t1);
tcg_temp_free_i32(zero);
tcg_gen_sub2_i32(t2, t1, tcg_constant_i32(0), t3, t2, t1);
} else {
tcg_gen_add_i32(t1, t1, t3);
}
@ -8118,7 +8050,7 @@ static bool op_stm(DisasContext *s, arg_ldst_block *a, int min_n)
{
int i, j, n, list, mem_idx;
bool user = a->u;
TCGv_i32 addr, tmp, tmp2;
TCGv_i32 addr, tmp;
if (user) {
/* STM (user) */
@ -8148,9 +8080,7 @@ static bool op_stm(DisasContext *s, arg_ldst_block *a, int min_n)
if (user && i != 15) {
tmp = tcg_temp_new_i32();
tmp2 = tcg_const_i32(i);
gen_helper_get_user_reg(tmp, cpu_env, tmp2);
tcg_temp_free_i32(tmp2);
gen_helper_get_user_reg(tmp, cpu_env, tcg_constant_i32(i));
} else {
tmp = load_reg(s, i);
}
@ -8191,7 +8121,7 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a, int min_n)
bool loaded_base;
bool user = a->u;
bool exc_return = false;
TCGv_i32 addr, tmp, tmp2, loaded_var;
TCGv_i32 addr, tmp, loaded_var;
if (user) {
/* LDM (user), LDM (exception return) */
@ -8234,9 +8164,7 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a, int min_n)
tmp = tcg_temp_new_i32();
gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
if (user) {
tmp2 = tcg_const_i32(i);
gen_helper_set_user_reg(cpu_env, tmp2, tmp);
tcg_temp_free_i32(tmp2);
gen_helper_set_user_reg(cpu_env, tcg_constant_i32(i), tmp);
tcg_temp_free_i32(tmp);
} else if (i == a->rn) {
loaded_var = tmp;
@ -8329,7 +8257,7 @@ static bool trans_CLRM(DisasContext *s, arg_CLRM *a)
s->eci_handled = true;
zero = tcg_const_i32(0);
zero = tcg_constant_i32(0);
for (i = 0; i < 15; i++) {
if (extract32(a->list, i, 1)) {
/* Clear R[i] */
@ -8341,11 +8269,8 @@ static bool trans_CLRM(DisasContext *s, arg_CLRM *a)
* Clear APSR (by calling the MSR helper with the same argument
* as for "MSR APSR_nzcvqg, Rn": mask = 0b1100, SYSM=0)
*/
TCGv_i32 maskreg = tcg_const_i32(0xc << 8);
gen_helper_v7m_msr(cpu_env, maskreg, zero);
tcg_temp_free_i32(maskreg);
gen_helper_v7m_msr(cpu_env, tcg_constant_i32(0xc00), zero);
}
tcg_temp_free_i32(zero);
clear_eci_state(s);
return true;
}
@ -8488,8 +8413,7 @@ static bool trans_DLS(DisasContext *s, arg_DLS *a)
store_reg(s, 14, tmp);
if (a->size != 4) {
/* DLSTP: set FPSCR.LTPSIZE */
tmp = tcg_const_i32(a->size);
store_cpu_field(tmp, v7m.ltpsize);
store_cpu_field(tcg_constant_i32(a->size), v7m.ltpsize);
s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
}
return true;
@ -8554,8 +8478,7 @@ static bool trans_WLS(DisasContext *s, arg_WLS *a)
*/
bool ok = vfp_access_check(s);
assert(ok);
tmp = tcg_const_i32(a->size);
store_cpu_field(tmp, v7m.ltpsize);
store_cpu_field(tcg_constant_i32(a->size), v7m.ltpsize);
/*
* LTPSIZE updated, but MVE_NO_PRED will always be the same thing (0)
* when we take this upcoming exit from this TB, so gen_jmp_tb() is OK.
@ -8681,8 +8604,7 @@ static bool trans_LE(DisasContext *s, arg_LE *a)
gen_set_label(loopend);
if (a->tp) {
/* Exits from tail-pred loops must reset LTPSIZE to 4 */
tmp = tcg_const_i32(4);
store_cpu_field(tmp, v7m.ltpsize);
store_cpu_field(tcg_constant_i32(4), v7m.ltpsize);
}
/* End TB, continuing to following insn */
gen_jmp_tb(s, s->base.pc_next, 1);
@ -8913,21 +8835,18 @@ static bool trans_CPS_v7m(DisasContext *s, arg_CPS_v7m *a)
return true;
}
tmp = tcg_const_i32(a->im);
tmp = tcg_constant_i32(a->im);
/* FAULTMASK */
if (a->F) {
addr = tcg_const_i32(19);
addr = tcg_constant_i32(19);
gen_helper_v7m_msr(cpu_env, addr, tmp);
tcg_temp_free_i32(addr);
}
/* PRIMASK */
if (a->I) {
addr = tcg_const_i32(16);
addr = tcg_constant_i32(16);
gen_helper_v7m_msr(cpu_env, addr, tmp);
tcg_temp_free_i32(addr);
}
gen_rebuild_hflags(s, false);
tcg_temp_free_i32(tmp);
gen_lookup_tb(s);
return true;
}
@ -9063,13 +8982,14 @@ static bool trans_CSEL(DisasContext *s, arg_CSEL *a)
}
/* In this insn input reg fields of 0b1111 mean "zero", not "PC" */
zero = tcg_constant_i32(0);
if (a->rn == 15) {
rn = tcg_const_i32(0);
rn = zero;
} else {
rn = load_reg(s, a->rn);
}
if (a->rm == 15) {
rm = tcg_const_i32(0);
rm = zero;
} else {
rm = load_reg(s, a->rm);
}
@ -9091,10 +9011,8 @@ static bool trans_CSEL(DisasContext *s, arg_CSEL *a)
}
arm_test_cc(&c, a->fcond);
zero = tcg_const_i32(0);
tcg_gen_movcond_i32(c.cond, rn, c.value, zero, rn, rm);
arm_free_cc(&c);
tcg_temp_free_i32(zero);
store_reg(s, a->rd, rn);
tcg_temp_free_i32(rm);