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target-microblaze: Tidy up the base-vectors property 

Rename the "xlnx.base-vectors" string to "base-vectors" and
move the base_vectors variable into the cfg struct.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
This commit is contained in:
Alistair Francis 2015-05-29 16:31:20 +10:00 committed by Edgar E. Iglesias
parent 9aaaa18194
commit f27183abaa
3 changed files with 8 additions and 7 deletions
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3
target-microblaze/cpu-qom.h
View File

@ -56,12 +56,13 @@ typedef struct MicroBlazeCPUClass {
typedef struct MicroBlazeCPU { typedef struct MicroBlazeCPU {
/*< private >*/ /*< private >*/
CPUState parent_obj; CPUState parent_obj;
uint32_t base_vectors;
/*< public >*/ /*< public >*/
/* Microblaze Configuration Settings */ /* Microblaze Configuration Settings */
struct { struct {
bool stackprot; bool stackprot;
uint32_t base_vectors;
} cfg; } cfg;
CPUMBState env; CPUMBState env;

4
target-microblaze/cpu.c
View File

@ -120,7 +120,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */ env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */
env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17); env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
env->sregs[SR_PC] = cpu->base_vectors; env->sregs[SR_PC] = cpu->cfg.base_vectors;
#if defined(CONFIG_USER_ONLY) #if defined(CONFIG_USER_ONLY)
env->pvr.regs[10] = 0x0c000000; /* Spartan 3a dsp. */ env->pvr.regs[10] = 0x0c000000; /* Spartan 3a dsp. */
@ -158,7 +158,7 @@ static const VMStateDescription vmstate_mb_cpu = {
}; };
static Property mb_properties[] = { static Property mb_properties[] = {
DEFINE_PROP_UINT32("xlnx.base-vectors", MicroBlazeCPU, base_vectors, 0), DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0),
DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot, DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot,
true), true),
DEFINE_PROP_END_OF_LIST(), DEFINE_PROP_END_OF_LIST(),

8
target-microblaze/helper.c
View File

@ -154,7 +154,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
env->sregs[SR_ESR], env->iflags); env->sregs[SR_ESR], env->iflags);
log_cpu_state_mask(CPU_LOG_INT, cs, 0); log_cpu_state_mask(CPU_LOG_INT, cs, 0);
env->iflags &= ~(IMM_FLAG | D_FLAG); env->iflags &= ~(IMM_FLAG | D_FLAG);
env->sregs[SR_PC] = cpu->base_vectors + 0x20; env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x20;
break; break;
case EXCP_MMU: case EXCP_MMU:
@ -194,7 +194,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
env->sregs[SR_PC], env->sregs[SR_EAR], env->iflags); env->sregs[SR_PC], env->sregs[SR_EAR], env->iflags);
log_cpu_state_mask(CPU_LOG_INT, cs, 0); log_cpu_state_mask(CPU_LOG_INT, cs, 0);
env->iflags &= ~(IMM_FLAG | D_FLAG); env->iflags &= ~(IMM_FLAG | D_FLAG);
env->sregs[SR_PC] = cpu->base_vectors + 0x20; env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x20;
break; break;
case EXCP_IRQ: case EXCP_IRQ:
@ -235,7 +235,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
env->sregs[SR_MSR] |= t; env->sregs[SR_MSR] |= t;
env->regs[14] = env->sregs[SR_PC]; env->regs[14] = env->sregs[SR_PC];
env->sregs[SR_PC] = cpu->base_vectors + 0x10; env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x10;
//log_cpu_state_mask(CPU_LOG_INT, cs, 0); //log_cpu_state_mask(CPU_LOG_INT, cs, 0);
break; break;
@ -254,7 +254,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
if (cs->exception_index == EXCP_HW_BREAK) { if (cs->exception_index == EXCP_HW_BREAK) {
env->regs[16] = env->sregs[SR_PC]; env->regs[16] = env->sregs[SR_PC];
env->sregs[SR_MSR] |= MSR_BIP; env->sregs[SR_MSR] |= MSR_BIP;
env->sregs[SR_PC] = cpu->base_vectors + 0x18; env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x18;
} else } else
env->sregs[SR_PC] = env->btarget; env->sregs[SR_PC] = env->btarget;
break; break;