openkylin
/
qemu
mirror of https://gitee.com/openkylin/qemu.git
9
0
Fork 0
Code Issues Projects Releases Wiki Activity

target/arm: make ARMCPU.clidr 64-bit 

The AArch64 view of CLIDR_EL1 extends the ICB field to include also bit
32, as well as adding a Ttype<n> field when FEAT_MTE is implemented.
Extend the clidr field to be able to hold this context.

Signed-off-by: Leif Lindholm <leif@nuviainc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20210108185154.8108-3-leif@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Leif Lindholm 2021-01-08 18:51:50 +00:00 committed by Peter Maydell
parent 9a286bcdfd
commit f6450bcb6b
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
target/arm/cpu.h
View File

@ -938,7 +938,7 @@ struct ARMCPU {
uint32_t id_afr0; uint32_t id_afr0;
uint64_t id_aa64afr0; uint64_t id_aa64afr0;
uint64_t id_aa64afr1; uint64_t id_aa64afr1;
uint32_t clidr; uint64_t clidr;
uint64_t mp_affinity; /* MP ID without feature bits */ uint64_t mp_affinity; /* MP ID without feature bits */
/* The elements of this array are the CCSIDR values for each cache, /* The elements of this array are the CCSIDR values for each cache,
* in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.