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ARM: Fix decoding of Neon forms of VCVT between float and fixed point 

Fix errors in the decoding of the Neon forms of fixed-point VCVT:
 * fixed-point VCVT is op 14 and 15, not 15 and 16
 * the fbits immediate field was being misinterpreted
 * the sense of the to_fixed bit was inverted

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
This commit is contained in:
Peter Maydell 2010-12-07 15:37:34 +00:00
parent 04595bf66f
commit f73534a56e
1 changed files with 6 additions and 2 deletions
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8
target-arm/translate.c
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@ -4850,11 +4850,15 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
}
neon_store_reg64(cpu_V0, rd + pass);
}
} else if (op == 15 || op == 16) {
} else if (op >= 14) {
/* VCVT fixed-point. */
/* We have already masked out the must-be-1 top bit of imm6,
* hence this 32-shift where the ARM ARM has 64-imm6.
*/
shift = 32 - shift;
for (pass = 0; pass < (q ? 4 : 2); pass++) {
tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, pass));
if (op & 1) {
if (!(op & 1)) {
if (u)
gen_vfp_ulto(0, shift);
else