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target/riscv: Don't overwrite the reset vector 

The reset vector is set in the init function don't set it again in
realize.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
This commit is contained in:
Alistair Francis 2020-05-19 11:04:12 -07:00
parent 757e99b1eb
commit f92d46ad07
1 changed files with 2 additions and 1 deletions
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3
target/riscv/cpu.c
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@ -133,6 +133,7 @@ static void riscv_base32_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
/* We set this in the realise function */
set_misa(env, 0);
set_resetvec(env, DEFAULT_RSTVEC);
}
static void rv32gcsu_priv1_10_0_cpu_init(Object *obj)
@ -170,6 +171,7 @@ static void riscv_base64_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
/* We set this in the realise function */
set_misa(env, 0);
set_resetvec(env, DEFAULT_RSTVEC);
}
static void rv64gcsu_priv1_10_0_cpu_init(Object *obj)
@ -377,7 +379,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
}
set_priv_version(env, priv_version);
set_resetvec(env, DEFAULT_RSTVEC);
if (cpu->cfg.mmu) {
set_feature(env, RISCV_FEATURE_MMU);