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i386/cpu_dump: support AVX512 ZMM regs dump 

Since commit fa4518741e (target-i386: Rename struct XMMReg to ZMMReg),
CPUX86State.xmm_regs[] has already been extended to 512bit to support
AVX512.
Also, other qemu level supports for AVX512 registers are there for
years.
But in x86_cpu_dump_state(), still only dump XMM registers no matter
YMM/ZMM is enabled.
This patch is to complement this, let it dump XMM/YMM/ZMM accordingly.

Signed-off-by: Robert Hoo <robert.hu@linux.intel.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1618986232-73826-1-git-send-email-robert.hu@linux.intel.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
This commit is contained in:
Robert Hoo 2021-04-21 14:23:52 +08:00 committed by Eduardo Habkost
parent e11fd68996
commit f9c0322a5f
1 changed files with 48 additions and 15 deletions
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63
target/i386/cpu-dump.c
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@ -478,6 +478,11 @@ void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags)
qemu_fprintf(f, "EFER=%016" PRIx64 "\n", env->efer); qemu_fprintf(f, "EFER=%016" PRIx64 "\n", env->efer);
if (flags & CPU_DUMP_FPU) { if (flags & CPU_DUMP_FPU) {
int fptag; int fptag;
const uint64_t avx512_mask = XSTATE_OPMASK_MASK | \
XSTATE_ZMM_Hi256_MASK | \
XSTATE_Hi16_ZMM_MASK | \
XSTATE_YMM_MASK | XSTATE_SSE_MASK,
avx_mask = XSTATE_YMM_MASK | XSTATE_SSE_MASK;
fptag = 0; fptag = 0;
for(i = 0; i < 8; i++) { for(i = 0; i < 8; i++) {
fptag |= ((!env->fptags[i]) << i); fptag |= ((!env->fptags[i]) << i);
@ -499,21 +504,49 @@ void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags)
else else
qemu_fprintf(f, " "); qemu_fprintf(f, " ");
} }
if (env->hflags & HF_CS64_MASK)
nb = 16; if ((env->xcr0 & avx512_mask) == avx512_mask) {
else /* XSAVE enabled AVX512 */
nb = 8; for (i = 0; i < NB_OPMASK_REGS; i++) {
for(i=0;i<nb;i++) { qemu_fprintf(f, "Opmask%02d=%016"PRIx64"%s", i,
qemu_fprintf(f, "XMM%02d=%08x%08x%08x%08x", env->opmask_regs[i], ((i & 3) == 3) ? "\n" : " ");
i, }
env->xmm_regs[i].ZMM_L(3),
env->xmm_regs[i].ZMM_L(2), nb = (env->hflags & HF_CS64_MASK) ? 32 : 8;
env->xmm_regs[i].ZMM_L(1), for (i = 0; i < nb; i++) {
env->xmm_regs[i].ZMM_L(0)); qemu_fprintf(f, "ZMM%02d=%016"PRIx64" %016"PRIx64" %016"PRIx64
if ((i & 1) == 1) " %016"PRIx64" %016"PRIx64" %016"PRIx64
qemu_fprintf(f, "\n"); " %016"PRIx64" %016"PRIx64"\n",
else i,
qemu_fprintf(f, " "); env->xmm_regs[i].ZMM_Q(7),
env->xmm_regs[i].ZMM_Q(6),
env->xmm_regs[i].ZMM_Q(5),
env->xmm_regs[i].ZMM_Q(4),
env->xmm_regs[i].ZMM_Q(3),
env->xmm_regs[i].ZMM_Q(2),
env->xmm_regs[i].ZMM_Q(1),
env->xmm_regs[i].ZMM_Q(0));
}
} else if ((env->xcr0 & avx_mask) == avx_mask) {
/* XSAVE enabled AVX */
nb = env->hflags & HF_CS64_MASK ? 16 : 8;
for (i = 0; i < nb; i++) {
qemu_fprintf(f, "YMM%02d=%016"PRIx64" %016"PRIx64" %016"PRIx64
" %016"PRIx64"\n", i,
env->xmm_regs[i].ZMM_Q(3),
env->xmm_regs[i].ZMM_Q(2),
env->xmm_regs[i].ZMM_Q(1),
env->xmm_regs[i].ZMM_Q(0));
}
} else { /* SSE and below cases */
nb = env->hflags & HF_CS64_MASK ? 16 : 8;
for (i = 0; i < nb; i++) {
qemu_fprintf(f, "XMM%02d=%016"PRIx64" %016"PRIx64"%s",
i,
env->xmm_regs[i].ZMM_Q(1),
env->xmm_regs[i].ZMM_Q(0),
(i & 1) ? "\n" : " ");
}
} }
} }
if (flags & CPU_DUMP_CODE) { if (flags & CPU_DUMP_CODE) {