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target/mips: Increase 'supported ISAs/ASEs' flag holder size 

Increase the size of insn_flags holder size to 64 bits. This is
needed for future extensions since existing bits are almost all used.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
This commit is contained in:
Philippe Mathieu-Daudé 2018-10-16 11:52:35 +02:00 committed by Aleksandar Markovic
parent 8bacd1ffc7
commit f9c9cd63e3
3 changed files with 5 additions and 5 deletions
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2
target/mips/cpu.h
View File

@ -811,7 +811,7 @@ struct CPUMIPSState {
int CCRes; /* Cycle count resolution/divisor */ int CCRes; /* Cycle count resolution/divisor */
uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */ uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */ uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
int insn_flags; /* Supported instruction set */ uint64_t insn_flags; /* Supported instruction set */
/* Fields up to this point are cleared by a CPU reset */ /* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields; struct {} end_reset_fields;

2
target/mips/internal.h
View File

@ -59,7 +59,7 @@ struct mips_def_t {
int32_t CP0_PageGrain_rw_bitmask; int32_t CP0_PageGrain_rw_bitmask;
int32_t CP0_PageGrain; int32_t CP0_PageGrain;
target_ulong CP0_EBaseWG_rw_bitmask; target_ulong CP0_EBaseWG_rw_bitmask;
int insn_flags; uint64_t insn_flags;
enum mips_mmu_types mmu_type; enum mips_mmu_types mmu_type;
}; };

6
target/mips/translate.c
View File

@ -1986,7 +1986,7 @@ typedef struct DisasContext {
target_ulong saved_pc; target_ulong saved_pc;
target_ulong page_start; target_ulong page_start;
uint32_t opcode; uint32_t opcode;
int insn_flags; uint64_t insn_flags;
int32_t CP0_Config1; int32_t CP0_Config1;
int32_t CP0_Config3; int32_t CP0_Config3;
int32_t CP0_Config5; int32_t CP0_Config5;
@ -2409,7 +2409,7 @@ static inline void check_dspr2(DisasContext *ctx)
/* This code generates a "reserved instruction" exception if the /* This code generates a "reserved instruction" exception if the
CPU does not support the instruction set corresponding to flags. */ CPU does not support the instruction set corresponding to flags. */
static inline void check_insn(DisasContext *ctx, int flags) static inline void check_insn(DisasContext *ctx, uint64_t flags)
{ {
if (unlikely(!(ctx->insn_flags & flags))) { if (unlikely(!(ctx->insn_flags & flags))) {
generate_exception_end(ctx, EXCP_RI); generate_exception_end(ctx, EXCP_RI);
@ -2419,7 +2419,7 @@ static inline void check_insn(DisasContext *ctx, int flags)
/* This code generates a "reserved instruction" exception if the /* This code generates a "reserved instruction" exception if the
CPU has corresponding flag set which indicates that the instruction CPU has corresponding flag set which indicates that the instruction
has been removed. */ has been removed. */
static inline void check_insn_opc_removed(DisasContext *ctx, int flags) static inline void check_insn_opc_removed(DisasContext *ctx, uint64_t flags)
{ {
if (unlikely(ctx->insn_flags & flags)) { if (unlikely(ctx->insn_flags & flags)) {
generate_exception_end(ctx, EXCP_RI); generate_exception_end(ctx, EXCP_RI);