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PPC: 405: Use proper CPU reset 

On ppc405ep there is a register that allows for software to reset the
core, but not the whole system. Implement this reset using a reset
interrupt.

This gets rid of a bunch of #if 0'ed code.

Reported-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
This commit is contained in:
Alexander Graf 2012-02-21 19:41:59 +01:00 committed by Andreas Färber
parent 418ba9e5d6
commit fc0b2c0f1a
4 changed files with 7 additions and 27 deletions
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2
cpu-exec.c
View File

@ -339,11 +339,9 @@ int cpu_exec(CPUState *env)
}
}
#elif defined(TARGET_PPC)
#if 0
if ((interrupt_request & CPU_INTERRUPT_RESET)) {
cpu_reset(env);
}
#endif
if (interrupt_request & CPU_INTERRUPT_HARD) {
ppc_hw_interrupt(env);
if (env->pending_interrupts == 0)

13
hw/ppc.c
View File

@ -131,13 +131,7 @@ static void ppc6xx_set_irq (void *opaque, int pin, int level)
/* Level sensitive - active low */
if (level) {
LOG_IRQ("%s: reset the CPU\n", __func__);
env->interrupt_request |= CPU_INTERRUPT_EXITTB;
/* XXX: TOFIX */
#if 0
cpu_reset(env);
#else
qemu_system_reset_request();
#endif
cpu_interrupt(env, CPU_INTERRUPT_RESET);
}
break;
case PPC6xx_INPUT_SRESET:
@ -214,10 +208,7 @@ static void ppc970_set_irq (void *opaque, int pin, int level)
case PPC970_INPUT_HRESET:
/* Level sensitive - active low */
if (level) {
#if 0 // XXX: TOFIX
LOG_IRQ("%s: reset the CPU\n", __func__);
cpu_reset(env);
#endif
cpu_interrupt(env, CPU_INTERRUPT_RESET);
}
break;
case PPC970_INPUT_SRESET:

16
hw/ppc405_uc.c
View File

@ -1769,13 +1769,7 @@ void ppc40x_core_reset (CPUState *env)
target_ulong dbsr;
printf("Reset PowerPC core\n");
env->interrupt_request |= CPU_INTERRUPT_EXITTB;
/* XXX: TOFIX */
#if 0
cpu_reset(env);
#else
qemu_system_reset_request();
#endif
cpu_interrupt(env, CPU_INTERRUPT_RESET);
dbsr = env->spr[SPR_40x_DBSR];
dbsr &= ~0x00000300;
dbsr |= 0x00000100;
@ -1787,13 +1781,7 @@ void ppc40x_chip_reset (CPUState *env)
target_ulong dbsr;
printf("Reset PowerPC chip\n");
env->interrupt_request |= CPU_INTERRUPT_EXITTB;
/* XXX: TOFIX */
#if 0
cpu_reset(env);
#else
qemu_system_reset_request();
#endif
cpu_interrupt(env, CPU_INTERRUPT_RESET);
/* XXX: TODO reset all internal peripherals */
dbsr = env->spr[SPR_40x_DBSR];
dbsr &= ~0x00000300;

3
target-ppc/cpu.h
View File

@ -2051,6 +2051,9 @@ enum {
PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
};
/* CPU should be reset next, restart from scratch afterwards */
#define CPU_INTERRUPT_RESET CPU_INTERRUPT_TGT_INT_0
/*****************************************************************************/
static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,