mirror of https://gitee.com/openkylin/qemu.git
target/mips: Add loongson-ext lswc2 group of instructions (Part 2)
LWC2 & SWC2 have been rewritten by Loongson EXT vendor ASE as "load/store quad word" and "shifted load/store" groups of instructions. This patch add implementation of these instructions: gslwlc1: similar to lwl but RT is FPR instead of GPR gslwrc1: similar to lwr but RT is FPR instead of GPR gsldlc1: similar to ldl but RT is FPR instead of GPR gsldrc1: similar to ldr but RT is FPR instead of GPR gsswlc1: similar to swl but RT is FPR instead of GPR gsswrc1: similar to swr but RT is FPR instead of GPR gssdlc1: similar to sdl but RT is FPR instead of GPR gssdrc1: similar to sdr but RT is FPR instead of GPR Details of Loongson-EXT is here: https://github.com/FlyGoat/loongson-insn/blob/master/loongson-ext.md Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhc@lemote.com> Message-Id: <1602831120-3377-4-git-send-email-chenhc@lemote.com> [PMD: Reuse t1 on MIPS32, reintroduce t2/fp0] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
Jiaxun Yang
Philippe Mathieu-Daudé
parent
e10a0ca17d
commit
fd723105c1
target/mips
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@ -471,6 +471,19 @@ enum {
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OPC_GSSHFS = OPC_SWC2,
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};
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/* Loongson EXT shifted load/store opcodes */
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#define MASK_LOONGSON_GSSHFLS(op) (MASK_OP_MAJOR(op) | (op & 0xc03f))
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enum {
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OPC_GSLWLC1 = 0x4 | OPC_GSSHFL,
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OPC_GSLWRC1 = 0x5 | OPC_GSSHFL,
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OPC_GSLDLC1 = 0x6 | OPC_GSSHFL,
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OPC_GSLDRC1 = 0x7 | OPC_GSSHFL,
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OPC_GSSWLC1 = 0x4 | OPC_GSSHFS,
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OPC_GSSWRC1 = 0x5 | OPC_GSSHFS,
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OPC_GSSDLC1 = 0x6 | OPC_GSSHFS,
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OPC_GSSDRC1 = 0x7 | OPC_GSSHFS,
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};
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/* BSHFL opcodes */
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#define MASK_BSHFL(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
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@ -5924,12 +5937,13 @@ no_rd:
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static void gen_loongson_lswc2(DisasContext *ctx, int rt,
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int rs, int rd)
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{
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TCGv t0;
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TCGv t0, t1, t2;
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TCGv_i32 fp0;
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#if defined(TARGET_MIPS64)
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TCGv t1;
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int lsq_rt1 = ctx->opcode & 0x1f;
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int lsq_offset = sextract32(ctx->opcode, 6, 9) << 4;
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#endif
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int shf_offset = sextract32(ctx->opcode, 6, 8);
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t0 = tcg_temp_new();
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@ -5986,6 +6000,170 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
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tcg_temp_free(t1);
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break;
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#endif
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case OPC_GSSHFL:
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switch (MASK_LOONGSON_GSSHFLS(ctx->opcode)) {
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case OPC_GSLWLC1:
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check_cp1_enabled(ctx);
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gen_base_offset_addr(ctx, t0, rs, shf_offset);
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t1 = tcg_temp_new();
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tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
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tcg_gen_andi_tl(t1, t0, 3);
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#ifndef TARGET_WORDS_BIGENDIAN
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tcg_gen_xori_tl(t1, t1, 3);
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#endif
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tcg_gen_shli_tl(t1, t1, 3);
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tcg_gen_andi_tl(t0, t0, ~3);
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tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL);
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tcg_gen_shl_tl(t0, t0, t1);
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t2 = tcg_const_tl(-1);
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tcg_gen_shl_tl(t2, t2, t1);
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fp0 = tcg_temp_new_i32();
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gen_load_fpr32(ctx, fp0, rt);
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tcg_gen_ext_i32_tl(t1, fp0);
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tcg_gen_andc_tl(t1, t1, t2);
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tcg_temp_free(t2);
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tcg_gen_or_tl(t0, t0, t1);
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tcg_temp_free(t1);
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#if defined(TARGET_MIPS64)
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tcg_gen_extrl_i64_i32(fp0, t0);
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#else
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tcg_gen_ext32s_tl(fp0, t0);
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#endif
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gen_store_fpr32(ctx, fp0, rt);
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tcg_temp_free_i32(fp0);
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break;
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case OPC_GSLWRC1:
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check_cp1_enabled(ctx);
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gen_base_offset_addr(ctx, t0, rs, shf_offset);
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t1 = tcg_temp_new();
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tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
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tcg_gen_andi_tl(t1, t0, 3);
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#ifdef TARGET_WORDS_BIGENDIAN
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tcg_gen_xori_tl(t1, t1, 3);
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#endif
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tcg_gen_shli_tl(t1, t1, 3);
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tcg_gen_andi_tl(t0, t0, ~3);
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tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL);
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tcg_gen_shr_tl(t0, t0, t1);
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tcg_gen_xori_tl(t1, t1, 31);
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t2 = tcg_const_tl(0xfffffffeull);
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tcg_gen_shl_tl(t2, t2, t1);
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fp0 = tcg_temp_new_i32();
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gen_load_fpr32(ctx, fp0, rt);
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tcg_gen_ext_i32_tl(t1, fp0);
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tcg_gen_and_tl(t1, t1, t2);
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tcg_temp_free(t2);
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tcg_gen_or_tl(t0, t0, t1);
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tcg_temp_free(t1);
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#if defined(TARGET_MIPS64)
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tcg_gen_extrl_i64_i32(fp0, t0);
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#else
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tcg_gen_ext32s_tl(fp0, t0);
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#endif
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gen_store_fpr32(ctx, fp0, rt);
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tcg_temp_free_i32(fp0);
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break;
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#if defined(TARGET_MIPS64)
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case OPC_GSLDLC1:
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check_cp1_enabled(ctx);
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gen_base_offset_addr(ctx, t0, rs, shf_offset);
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t1 = tcg_temp_new();
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tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
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tcg_gen_andi_tl(t1, t0, 7);
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#ifndef TARGET_WORDS_BIGENDIAN
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tcg_gen_xori_tl(t1, t1, 7);
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#endif
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tcg_gen_shli_tl(t1, t1, 3);
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tcg_gen_andi_tl(t0, t0, ~7);
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tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ);
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tcg_gen_shl_tl(t0, t0, t1);
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t2 = tcg_const_tl(-1);
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tcg_gen_shl_tl(t2, t2, t1);
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gen_load_fpr64(ctx, t1, rt);
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tcg_gen_andc_tl(t1, t1, t2);
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tcg_temp_free(t2);
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tcg_gen_or_tl(t0, t0, t1);
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tcg_temp_free(t1);
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gen_store_fpr64(ctx, t0, rt);
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break;
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case OPC_GSLDRC1:
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check_cp1_enabled(ctx);
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gen_base_offset_addr(ctx, t0, rs, shf_offset);
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t1 = tcg_temp_new();
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tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
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tcg_gen_andi_tl(t1, t0, 7);
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#ifdef TARGET_WORDS_BIGENDIAN
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tcg_gen_xori_tl(t1, t1, 7);
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#endif
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tcg_gen_shli_tl(t1, t1, 3);
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tcg_gen_andi_tl(t0, t0, ~7);
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tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ);
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tcg_gen_shr_tl(t0, t0, t1);
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tcg_gen_xori_tl(t1, t1, 63);
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t2 = tcg_const_tl(0xfffffffffffffffeull);
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tcg_gen_shl_tl(t2, t2, t1);
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gen_load_fpr64(ctx, t1, rt);
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tcg_gen_and_tl(t1, t1, t2);
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tcg_temp_free(t2);
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tcg_gen_or_tl(t0, t0, t1);
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tcg_temp_free(t1);
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gen_store_fpr64(ctx, t0, rt);
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break;
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#endif
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default:
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MIPS_INVAL("loongson_gsshfl");
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generate_exception_end(ctx, EXCP_RI);
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break;
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}
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break;
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case OPC_GSSHFS:
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switch (MASK_LOONGSON_GSSHFLS(ctx->opcode)) {
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case OPC_GSSWLC1:
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check_cp1_enabled(ctx);
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t1 = tcg_temp_new();
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gen_base_offset_addr(ctx, t0, rs, shf_offset);
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fp0 = tcg_temp_new_i32();
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gen_load_fpr32(ctx, fp0, rt);
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tcg_gen_ext_i32_tl(t1, fp0);
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gen_helper_0e2i(swl, t1, t0, ctx->mem_idx);
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tcg_temp_free_i32(fp0);
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tcg_temp_free(t1);
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break;
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case OPC_GSSWRC1:
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check_cp1_enabled(ctx);
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t1 = tcg_temp_new();
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gen_base_offset_addr(ctx, t0, rs, shf_offset);
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fp0 = tcg_temp_new_i32();
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gen_load_fpr32(ctx, fp0, rt);
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tcg_gen_ext_i32_tl(t1, fp0);
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gen_helper_0e2i(swr, t1, t0, ctx->mem_idx);
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tcg_temp_free_i32(fp0);
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tcg_temp_free(t1);
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break;
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#if defined(TARGET_MIPS64)
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case OPC_GSSDLC1:
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check_cp1_enabled(ctx);
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t1 = tcg_temp_new();
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gen_base_offset_addr(ctx, t0, rs, shf_offset);
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gen_load_fpr64(ctx, t1, rt);
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gen_helper_0e2i(sdl, t1, t0, ctx->mem_idx);
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tcg_temp_free(t1);
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break;
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case OPC_GSSDRC1:
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check_cp1_enabled(ctx);
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t1 = tcg_temp_new();
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gen_base_offset_addr(ctx, t0, rs, shf_offset);
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gen_load_fpr64(ctx, t1, rt);
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gen_helper_0e2i(sdr, t1, t0, ctx->mem_idx);
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tcg_temp_free(t1);
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break;
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#endif
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default:
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MIPS_INVAL("loongson_gsshfs");
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generate_exception_end(ctx, EXCP_RI);
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break;
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}
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break;
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default:
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MIPS_INVAL("loongson_gslsq");
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generate_exception_end(ctx, EXCP_RI);
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