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target/mips: Move msa_reset() to new source file 

mips_cpu_reset() is used by all accelerators, and calls
msa_reset(), which is defined in msa_helper.c.

Beside msa_reset(), the rest of msa_helper.c is only useful
to the TCG accelerator. To be able to restrict this helper
file to TCG, we need to move msa_reset() out of it.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210428170410.479308-4-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2021-01-16 16:32:06 +01:00
parent 830a72301c
commit fed50ffd5c
3 changed files with 61 additions and 36 deletions
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1
target/mips/meson.build
View File

@ -11,6 +11,7 @@ mips_ss.add(files(
'cpu.c',
'fpu.c',
'gdbstub.c',
'msa.c',
))
mips_tcg_ss = ss.source_set()
mips_tcg_ss.add(gen)

60
target/mips/msa.c Normal file
View File

@ -0,0 +1,60 @@
/*
* MIPS SIMD Architecture Module Instruction emulation helpers for QEMU.
*
* Copyright (c) 2014 Imagination Technologies
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "cpu.h"
#include "internal.h"
#include "fpu/softfloat.h"
#include "fpu_helper.h"
void msa_reset(CPUMIPSState *env)
{
if (!ase_msa_available(env)) {
return;
}
#ifdef CONFIG_USER_ONLY
/* MSA access enabled */
env->CP0_Config5 |= 1 << CP0C5_MSAEn;
env->CP0_Status |= (1 << CP0St_CU1) | (1 << CP0St_FR);
#endif
/*
* MSA CSR:
* - non-signaling floating point exception mode off (NX bit is 0)
* - Cause, Enables, and Flags are all 0
* - round to nearest / ties to even (RM bits are 0)
*/
env->active_tc.msacsr = 0;
restore_msa_fp_status(env);
/* tininess detected after rounding.*/
set_float_detect_tininess(float_tininess_after_rounding,
&env->active_tc.msa_fp_status);
/* clear float_status exception flags */
set_float_exception_flags(0, &env->active_tc.msa_fp_status);
/* clear float_status nan mode */
set_default_nan_mode(0, &env->active_tc.msa_fp_status);
/* set proper signanling bit meaning ("1" means "quiet") */
set_snan_bit_is_one(0, &env->active_tc.msa_fp_status);
}

36
target/mips/msa_helper.c
View File

@ -8595,39 +8595,3 @@ void helper_msa_st_d(CPUMIPSState *env, uint32_t wd,
cpu_stq_data(env, addr + (1 << DF_DOUBLE), pwd->d[1]);
#endif
}
void msa_reset(CPUMIPSState *env)
{
if (!ase_msa_available(env)) {
return;
}
#ifdef CONFIG_USER_ONLY
/* MSA access enabled */
env->CP0_Config5 |= 1 << CP0C5_MSAEn;
env->CP0_Status |= (1 << CP0St_CU1) | (1 << CP0St_FR);
#endif
/*
* MSA CSR:
* - non-signaling floating point exception mode off (NX bit is 0)
* - Cause, Enables, and Flags are all 0
* - round to nearest / ties to even (RM bits are 0)
*/
env->active_tc.msacsr = 0;
restore_msa_fp_status(env);
/* tininess detected after rounding.*/
set_float_detect_tininess(float_tininess_after_rounding,
&env->active_tc.msa_fp_status);
/* clear float_status exception flags */
set_float_exception_flags(0, &env->active_tc.msa_fp_status);
/* clear float_status nan mode */
set_default_nan_mode(0, &env->active_tc.msa_fp_status);
/* set proper signanling bit meaning ("1" means "quiet") */
set_snan_bit_is_one(0, &env->active_tc.msa_fp_status);
}