From ff8263a951c5ce22bef919c792d20e5cbf5066b3 Mon Sep 17 00:00:00 2001
From: bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162>
Date: Fri, 13 May 2005 22:45:23 +0000
Subject: [PATCH] ARM saturating arithmetic fixes (Paul Brook)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1431 c046a42c-6fe2-441c-8c8c-71466251a162
---
 target-arm/op.c        | 17 +++++++++++++++++
 target-arm/translate.c | 15 +++++----------
 2 files changed, 22 insertions(+), 10 deletions(-)

diff --git a/target-arm/op.c b/target-arm/op.c
index 0a3811ed2f..8a82def79a 100644
--- a/target-arm/op.c
+++ b/target-arm/op.c
@@ -805,6 +805,23 @@ void OPPROTO op_subl_T0_T1_saturate(void)
   FORCE_RET();
 }
 
+void OPPROTO op_double_T1_saturate(void)
+{
+  int32_t val;
+
+  val = T1;
+  if (val >= 0x40000000) {
+      T1 = 0x7fffffff;
+      env->QF = 1;
+  } else if (val <= (int32_t)0xc0000000) {
+      T1 = 0x80000000;
+      env->QF = 1;
+  } else {
+      T1 = val << 1;
+  }
+  FORCE_RET();
+}
+
 /* thumb shift by immediate */
 void OPPROTO op_shll_T0_im_thumb(void)
 {
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 29657416f3..2a62c56285 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -1019,20 +1019,15 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
         case 0x5: /* saturating add/subtract */
             rd = (insn >> 12) & 0xf;
             rn = (insn >> 16) & 0xf;
-            gen_movl_T0_reg(s, rn);
-            if (op1 & 2) {
-                gen_movl_T1_reg(s, rn);
-                if (op1 & 1) 
-                    gen_op_subl_T0_T1_saturate();
-                else
-                    gen_op_addl_T0_T1_saturate();
-            }
-            gen_movl_T1_reg(s, rm);
+            gen_movl_T0_reg(s, rm);
+            gen_movl_T1_reg(s, rn);
+            if (op1 & 2)
+                gen_op_double_T1_saturate();
             if (op1 & 1)
                 gen_op_subl_T0_T1_saturate();
             else
                 gen_op_addl_T0_T1_saturate();
-            gen_movl_reg_T0(s, rn);
+            gen_movl_reg_T0(s, rd);
             break;
         case 0x8: /* signed multiply */
         case 0xa: