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qemu
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2 Commits

Author SHA1 Message Date
Stafford Horne 0ca9fa2e3c openrisc/ompic: Add OpenRISC Multicore PIC (OMPIC) 
Add OpenRISC Multicore PIC which handles inter processor interrupts
(IPI) between cores.  In OpenRISC all device interrupts are routed to
each core enabling this device to be simple.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
 2017-10-21 06:35:47 +09:00
Richard Henderson 4a09d0bb34 target/openrisc: Rename the cpu from or32 to or1k 
This is in keeping with the toolchain and or1ksim.

Signed-off-by: Richard Henderson <rth@twiddle.net>
 2017-02-14 08:14:58 +11:00